公开(公告)号：US20150036418A1

公开(公告)日：2015-02-05

申请号：US14064297

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Satendra Kumar Maurya

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.

Abstract translation: 公开了在SRAM复位操作期间用于电压或电流偏置静态随机存取存储器（SRAM）位单元的电路。 还公开了相关系统和方法。 为了在单个复位操作中复位多个SRAM位单元，提供偏置电路并耦合到多个SRAM位单元。 偏置电路被配置为在复位操作期间向SRAM位单元施加电压或电流偏置，其中提供给SRAM位单元的功率被折叠到低于操作功率电平的压缩功率电平。 当SRAM位单元的功率恢复到工作功率电平时，施加偏压，从而迫使SRAM位单元进入所需状态。 以这种方式，可以在单个复位操作中复位SRAM位单元，而不需要来自复位电路的增加的驱动强度，而不需要提供专门的SRAM位单元。

公开(公告)号：US09190141B2

公开(公告)日：2015-11-17

申请号：US14064297

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Satendra Kumar Maurya

IPC: G11C11/00 ,  G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.

Abstract translation: 公开了在SRAM复位操作期间用于电压或电流偏置静态随机存取存储器（SRAM）位单元的电路。 还公开了相关系统和方法。 为了在单个复位操作中复位多个SRAM位单元，提供偏置电路并耦合到多个SRAM位单元。 偏置电路被配置为在复位操作期间向SRAM位单元施加电压或电流偏置，其中提供给SRAM位单元的功率被折叠到低于操作功率电平的压缩功率电平。 当SRAM位单元的功率恢复到工作功率电平时，施加偏压，从而迫使SRAM位单元进入所需状态。 以这种方式，可以在单个复位操作中复位SRAM位单元，而不需要来自复位电路的增加的驱动强度，而不需要提供专门的SRAM位单元。

公开(公告)号：US09548089B2

公开(公告)日：2017-01-17

申请号：US14742706

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Stephen Edward Liles ,  Satendra Kumar Maurya ,  Kunal Garg ,  Chiaming Chai ,  Chintan Shah

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract translation: 异步存储器包括存储器阵列，读出放大器，输出锁存器和控制器。 响应于来自外部电路的请求读取操作的时钟信号，控制器将时钟信号提供给存储器阵列以读取数据，并且控制读出放大器和输出锁存器以提供触发器主器件和从器件的功能 使得通过输出锁存器到外部电路的读操作延迟从两个顺序读周期的第一读周期中去除。