公开(公告)号：US20170047930A1

公开(公告)日：2017-02-16

申请号：US14827125

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Chintan Hemendrakumar Shah

IPC: H03K19/0185 ,  H03K19/20

CPC classification number: H03K19/018528 ,  H03K3/356121 ,  H03K19/0963 ,  H03K19/20

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.

Abstract translation: 公开了采用脉冲发生电路的动态电压电平移位器。 一方面，动态电压电平移位器包括动态电压电平移位电路。 动态电压电平移位电路包括预充电电路，其被配置为响应于具有预充电电压的时钟信号向动态节点提供第一电压域的电源电压。 评估电路被配置为当时钟信号具有评估电压时响应于具有有效电压的输入信号向动态节点提供接地电压。 保持器电路被配置为响应于脉冲信号向动态节点提供降低的驱动强度。 脉冲信号由脉冲发生电路产生，其中脉冲信号的脉冲宽度与第一和第二电压域的电源电压的差异相关。

公开(公告)号：US09608637B2

公开(公告)日：2017-03-28

申请号：US14827125

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Chintan Hemendrakumar Shah

IPC: H03K19/20 ,  H03K19/0185

CPC classification number: H03K19/018528 ,  H03K3/356121 ,  H03K19/0963 ,  H03K19/20

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.