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    Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits
    1.
    发明授权
    Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits 有权

    公开(公告)号：US10319425B1

    公开(公告)日：2019-06-11

    申请号：US15939514

    申请日：2018-03-29

    Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

    Inventor： Seong-Ook Jung ,  Byungkyu Song ,  Sungryul Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16

    Abstract: Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

    Offset canceling dual stage sensing circuit
    6.
    发明授权
    Offset canceling dual stage sensing circuit 有权
    偏移消除双级感测电路

    公开(公告)号：US09165630B2

    公开(公告)日：2015-10-20

    申请号：US14015845

    申请日：2013-08-30

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/00 ,  G11C11/16 ,  G11C7/06 ,  G11C13/00

    CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

    Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.

    Abstract translation: 偏移消除双级感测方法包括：在第一级操作中使用由电阻性存储器参考单元的参考值产生的第一负载PMOS栅极电压来感测电阻性存储器数据单元的数据值。 该方法还包括使用在电阻性存储器感测电路的第二级操作中由电阻性存储器数据单元的数据值产生的第二负载PMOS栅极电压来感测电阻性存储器参考单元的参考值。 通过调整参考单元感测的工作点，与常规感测电路相比，偏移消除双级感测电路显着增加了感测余量。

    SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT
    7.
    发明申请
    SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT 有权
    SRAM读取具有写入辅助电路的优选位单元

    公开(公告)号：US20140036578A1

    公开(公告)日：2014-02-06

    申请号：US13741869

    申请日：2013-01-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

    IPC: G11C11/412

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

    Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。

    LATCHING CIRCUIT
    8.
    发明申请
    LATCHING CIRCUIT 有权
    锁定电路

    公开(公告)号：US20130182500A1

    公开(公告)日：2013-07-18

    申请号：US13785338

    申请日：2013-03-05

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

    Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.

    Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过基于电阻的存储元件的电流。

    Seven-transistor static random-access memory bitcell with reduced read disturbance
    9.
    发明授权
    Seven-transistor static random-access memory bitcell with reduced read disturbance 有权

    公开(公告)号：US10037795B2

    公开(公告)日：2018-07-31

    申请号：US14499149

    申请日：2014-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

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