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1.发明授权Unified front-end receiver interface for accommodating incoming signals via AC-coupling or DC-coupling 有权统一的前端接收器接口，用于通过交流耦合或直流耦合来接收输入信号公开(公告)号：US09584184B2
公开(公告)日：2017-02-28
申请号：US13784821
申请日：2013-03-05
Applicant: QUALCOMM Incorporated
Inventor： Miao Li , Xiaohua Kong , Jingcheng Zhuang , Wei Wang
Abstract: Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.
Abstract translation: 这里描述了用于通过AC耦合或DC耦合在前端接收器处容纳输入信号的技术。 一方面，前端接收机包括具有第一数据线的差分输入和用于接收输入信号的第二数据线。 前端接收器还包括耦合到差分输入的AC耦合开关，其中AC耦合开关被配置为对输入信号执行高通滤波，并且通过DC偏移电压偏移滤波的输入信号，如果 接收器的AC耦合模式被使能。 前端接收器还包括耦合到差分输入的DC耦合开关，其中如果接收器的DC耦合模式被使能，则DC耦合开关被配置为移位输入信号的共模电压。
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2.发明授权Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL) 有权用于模拟锁相环（PLL）的无毛刺带宽切换方案公开(公告)号：US09520887B1
公开(公告)日：2016-12-13
申请号：US15060198
申请日：2016-03-03
Applicant: QUALCOMM Incorporated
Inventor： Jingcheng Zhuang , Jong Min Park , Lai Kan Leung , Yiwu Tang
CPC classification number: H03L7/093 , H03L7/099 , H03L7/1072 , H03L7/1075
Abstract: Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.
Abstract translation: 本公开的某些方面提供了在锁相环（PLL）中无毛刺带宽切换的技术和装置。 一个示例PLL通常包括包括第一可变电容元件和第二可变电容元件的压控振荡器（VCO），以及包括与电阻器 - 电容器（RC）网络的电阻器并联的第一开关的带宽调整电路。 带宽调整电路被配置为在第一带宽模式下打开第一开关，在从第一带宽模式到第二带宽模式的转变中关闭第一开关，并且基于第一可变电容元件的电压来控制第二可变电容元件的电容 RC网络的一个节点。
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公开(公告)号：US10116315B1
公开(公告)日：2018-10-30
申请号：US15711918
申请日：2017-09-21
Applicant: QUALCOMM Incorporated
Inventor： Jingcheng Zhuang , Frederic Bossu
Abstract: A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.
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公开(公告)号：US09864341B1
公开(公告)日：2018-01-09
申请号：US15368375
申请日：2016-12-02
Applicant: QUALCOMM Incorporated
Inventor： Jingcheng Zhuang
CPC classification number: G04F10/005
Abstract: An integrated circuit (IC) is disclosed for time-to-digital conversion with a latch-based ring. In example aspects, the IC includes a ring, a counter, an encoder, and time-to-digital converter (TDC) control circuitry. The ring includes multiple ring stages and propagates a ring signal between successive ring stages. Each respective ring stage includes latch circuitry to secure a state of the ring signal at the respective ring stage. The ring provides a ring output signal using the latch circuitry of each of the ring stages. The ring is coupled to the counter. The counter increments a counter value responsive to the ring signal and provides a counter output signal based on the counter value. The encoder is coupled to the ring and the counter. The encoder generates a TDC output signal based on the ring and counter output signals. The TDC control circuitry operates the ring responsive to a TDC input signal.
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公开(公告)号：US09176511B1
公开(公告)日：2015-11-03
申请号：US14254279
申请日：2014-04-16
Applicant: QUALCOMM Incorporated
Inventor： Nam Van Dang , Rajeev Jain , Terrence Brian Remple , Jingcheng Zhuang , Mong Chit Wong
Abstract: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.
Abstract translation: 提供了一系列具有局部反馈的电流中继器。 在串联中的随后的当前中继器之前的每个电流被配置为从随后的当前中继器接收反馈电流，并且相应地使用差分放大器产生误差信号，以便减少否则由于偏置电压而产生的电流重复误差 差分放大器。
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Patent Agency Ranking
公开(公告)号：US08970254B1
公开(公告)日：2015-03-03
申请号：US14195378
申请日：2014-03-03
Applicant: QUALCOMM Incorporated
Inventor： Glenn Murphy , Jingcheng Zhuang , Xiaohua Kong , William Knox Ladd
CPC classification number: H04L25/0262 , H04L25/4902
Abstract: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.
Abstract translation: 提供根据一个或多个实施例的方法和系统用于频率检测。 在一个实施例中，提供了一种频率检测器，其包括响应于输入信号的二进制状态而放电或充电的电容器。
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公开(公告)号：US10256796B2
公开(公告)日：2019-04-09
申请号：US15448657
申请日：2017-03-03
Applicant: QUALCOMM Incorporated
Inventor： Shih-Chieh Hsin , Med Nariman , Jingcheng Zhuang
IPC: H03K3/3562 , H03K19/0185 , H03K3/356
Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.
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8.发明授权公开(公告)号：US10177772B2
公开(公告)日：2019-01-08
申请号：US15272307
申请日：2016-09-21
Applicant: QUALCOMM Incorporated
Inventor： Jingcheng Zhuang , Xinhua Chen , Frederic Bossu , Yiwu Tang
Abstract: A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.
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公开(公告)号：US09998129B1
公开(公告)日：2018-06-12
申请号：US15711962
申请日：2017-09-21
Applicant: QUALCOMM Incorporated
Inventor： Jingcheng Zhuang , Jianyun Hu , Animesh Paul , Xinhua Chen , Frederic Bossu
CPC classification number: H03L7/1803 , H03C3/0975 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L7/197 , H03L7/1976 , H04L7/00 , H04L7/0008 , H04L7/033
Abstract: A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.
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公开(公告)号：US09893875B2
公开(公告)日：2018-02-13
申请号：US15270444
申请日：2016-09-20
Applicant: QUALCOMM Incorporated
Inventor： Marco Zanuso , Mohammad Elbadry , Tsai-Pi Hung , Ravi Sridhara , Francesco Gatta , Jingcheng Zhuang
CPC classification number: H04L7/033 , H03L7/14 , H03L7/143 , H03L7/1976 , H03L2207/08 , H04L5/14 , H04L69/28 , H04W84/042
Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.
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