公开(公告)号：US20180254772A1

公开(公告)日：2018-09-06

申请号：US15448657

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Shih-Chieh Hsin ,  Med Nariman ,  Jingcheng Zhuang

IPC: H03K3/3562 ,  H03K19/0185

CPC classification number: H03K3/35625 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/018521

Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.

公开(公告)号：US10256796B2

公开(公告)日：2019-04-09

申请号：US15448657

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Shih-Chieh Hsin ,  Med Nariman ,  Jingcheng Zhuang

IPC: H03K3/3562 ,  H03K19/0185 ,  H03K3/356

Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.