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    PHASE-LOCKED LOOP CIRCUIT CALIBRATION METHOD, MEMORY STORAGE DEVICE AND CONNECTION INTERFACE CIRCUIT
    2.
    发明申请
    PHASE-LOCKED LOOP CIRCUIT CALIBRATION METHOD, MEMORY STORAGE DEVICE AND CONNECTION INTERFACE CIRCUIT 审中-公开

    公开(公告)号：US20190288700A1

    公开(公告)日：2019-09-19

    申请号：US15973539

    申请日：2018-05-08

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chia-Hui Yu ,  Wei-Yung Chen

    IPC: H03L7/10 ,  H03L7/099 ,  G06F13/16 ,  G06F13/42

    Abstract: A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit.

    Clock adjusting circuit, memory storage device, and memory control circuit unit
    4.
    发明授权
    Clock adjusting circuit, memory storage device, and memory control circuit unit 有权
    时钟调节电路，存储器存储器件和存储器控制电路单元

    公开(公告)号：US09318155B2

    公开(公告)日：2016-04-19

    申请号：US14011773

    申请日：2013-08-28

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Yung Chen ,  Yan-An Lin

    IPC: G11C5/02 ,  G11C29/02 ,  G11C7/22 ,  H03L7/08 ,  H03L7/18

    CPC classification number: G11C5/025 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/08 ,  H03L7/18

    Abstract: A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced.

    Abstract translation: 提供了设置在多个层上的存储器存储装置，存储器控制电路单元和时钟调整电路。 时钟调整电路包括检测电路，控制电压产生电路和压控振荡器（VCO）。 检测电路检测输入信号和输出信号之间的信号特性差，以产生第一信号。 控制电压产生电路耦合到检测电路，并根据第一信号产生控制电压。 VCO耦合到控制电压产生电路并且包括电感器和电容器。 VCO接收控制电压，并根据电感器和电容器的阻抗特性开始振荡，以产生输出信号。 电感器设置在层之间的衬垫层上。 由此，制造成本降低。

    FREQUENCY GENERATING SYSTEM, VOLTAGE-CONTROLLED OSCILLATOR MODULE AND METHOD FOR ADJUSTING SIGNAL FREQUENCY
    5.
    发明申请
    FREQUENCY GENERATING SYSTEM, VOLTAGE-CONTROLLED OSCILLATOR MODULE AND METHOD FOR ADJUSTING SIGNAL FREQUENCY 有权
    频率发生系统，电压控制振荡器模块和调整信号频率的方法

    公开(公告)号：US20140049303A1

    公开(公告)日：2014-02-20

    申请号：US13646744

    申请日：2012-10-08

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Yung Chen

    IPC: H03L7/08

    CPC classification number: H03L7/18 ,  H03L7/089 ,  H03L2207/06

    Abstract: A voltage controlled oscillator module including a VCO unit and a gain adjustment unit is provided. The VCO unit is configured to generate a frequency signal based on a control voltage. The gain adjustment unit is coupled to the VCO unit and configured to receive a first adjustment voltage, a second adjustment voltage, and a reference voltage and accordingly adjusts the control voltage to adjust a frequency value of the frequency signal. The gain adjustment unit includes an adjustment circuit unit and a reference circuit unit. A first voltage-frequency curve of the frequency value of the frequency signal and a voltage value of the first adjustment voltage changes in response to a structure characteristic of the adjustment circuit unit. Furthermore, a frequency generating system and a method for adjusting a signal frequency of the VCO module are provided.

    Abstract translation: 提供了包括VCO单元和增益调节单元的压控振荡器模块。 VCO单元被配置为基于控制电压产生频率信号。 增益调整单元耦合到VCO单元并且被配置为接收第一调整电压，第二调整电压和参考电压，并且因此调整控制电压以调整频率信号的频率值。 增益调整单元包括调整电路单元和参考电路单元。 频率信号的频率值和第一调整电压的电压值的第一电压 - 频率曲线响应于调整电路单元的结构特性而改变。 此外，提供了用于调整VCO模块的信号频率的频率产生系统和方法。

    PHASE LOCK METHOD
    6.
    发明申请
    PHASE LOCK METHOD 审中-公开
    相位锁定方法

    公开(公告)号：US20160380639A1

    公开(公告)日：2016-12-29

    申请号：US15261877

    申请日：2016-09-10

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Yung Chen ,  Yu-Chiang Liao

    IPC: H03L7/08 ,  H03L7/087 ,  G11C7/22 ,  H03L7/099

    CPC classification number: H03L7/091 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/033

    Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.

    Abstract translation: 提供锁相方法。 该方法包括：根据多个参考时钟对数据信号进行采样并输出采样结果; 根据采样结果执行第一逻辑运算并输出第一逻辑结果; 延迟第一逻辑结果并输出延迟的第一逻辑结果; 根据第一逻辑结果和延迟的第一逻辑结果执行第二逻辑运算并输出第二逻辑结果; 根据第二逻辑结果输出第一频率调整信号; 以及根据第一频率调整信号和数据信号的频率执行锁相。

    Memory storage device having clock and data recovery circuit
    7.
    发明授权
    Memory storage device having clock and data recovery circuit 有权
    具有时钟和数据恢复电路的存储器

    公开(公告)号：US09479183B1

    公开(公告)日：2016-10-25

    申请号：US14745470

    申请日：2015-06-22

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Yung Chen ,  Yu-Chiang Liao

    IPC: G11C11/34 ,  G11C7/00 ,  G11C8/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H03L7/107 ,  G11C7/22

    CPC classification number: H03L7/091 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/033

    Abstract: A memory storage device having a clock and data recovery circuit module are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.

    Abstract translation: 提供了具有时钟和数据恢复电路模块的存储器存储装置。 模块包括采样电路，第一逻辑电路模块，延迟电路模块，第二逻辑电路模块，频率调整电路和时钟控制电路。 采样电路根据参考时钟采样数据信号。 第一逻辑电路模块根据采样结果进行第一逻辑运算。 延迟电路模块延迟第一逻辑运算的结果。 第二逻辑电路模块根据所述结果和延迟的第一逻辑结果执行第二逻辑运算。 频率调整电路根据第二逻辑运算的结果输出频率调整信号，并且时钟控制电路相应地执行相位锁定。 因此，可以减少时钟和数据恢复电路模块的电路复杂度。

    MEMORY STORAGE DEVICE HAVING CLOCK AND DATA RECOVERY CIRCUIT
    8.
    发明申请
    MEMORY STORAGE DEVICE HAVING CLOCK AND DATA RECOVERY CIRCUIT 有权
    具有时钟和数据恢复电路的存储器存储器件

    公开(公告)号：US20160308539A1

    公开(公告)日：2016-10-20

    申请号：US14745470

    申请日：2015-06-22

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Yung Chen ,  Yu-Chiang Liao

    IPC: H03L7/08 ,  G11C7/22 ,  H03L7/107 ,  H03L7/091 ,  H03L7/099

    CPC classification number: H03L7/091 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/033

    Abstract: A clock and data recovery circuit module, a memory storage device and a phase lock method are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.

    Abstract translation: 提供时钟和数据恢复电路模块，存储器存储装置和锁相方法。 模块包括采样电路，第一逻辑电路模块，延迟电路模块，第二逻辑电路模块，频率调整电路和时钟控制电路。 采样电路根据参考时钟采样数据信号。 第一逻辑电路模块根据采样结果进行第一逻辑运算。 延迟电路模块延迟第一逻辑运算的结果。 第二逻辑电路模块根据所述结果和延迟的第一逻辑结果执行第二逻辑运算。 频率调整电路根据第二逻辑运算的结果输出频率调整信号，并且时钟控制电路相应地执行相位锁定。 因此，可以减少时钟和数据恢复电路模块的电路复杂度。

    Controlling method for connector, connector and memory storage device
    9.
    发明授权
    Controlling method for connector, connector and memory storage device 有权
    连接器，连接器和存储器的控制方法

    公开(公告)号：US09081659B2

    公开(公告)日：2015-07-14

    申请号：US13692981

    申请日：2012-12-03

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Ming Chen ,  Wei-Yung Chen ,  Ming-Hui Tseng

    IPC: G06F1/32 ,  G06F12/02 ,  H04B1/16 ,  H04W52/02

    CPC classification number: G06F12/0238 ,  G06F1/3215 ,  G06F1/3278 ,  H04B1/1615 ,  H04W52/0229 ,  Y02D10/157 ,  Y02D70/00

    Abstract: A controlling method for connector is provided, which includes: receiving a first signal stream under a condition that a squelch detector is turned-off; determining whether the first signal stream contains a burst signal under a first operating frequency; if the first signal stream contains the burst signal, turning on the squelch detector and determining by the squelch detector under a second operating frequency whether a second signal stream is a waking signal, wherein the second signal stream is received after receiving the first signal stream and the second operating frequency is greater than the first operating frequency. The controlling method further includes: if the second signal stream is the waking signal, changing an operating state of the connector to an active state. In this way, the power consumption of the connector is reduced.

    Abstract translation: 提供了一种用于连接器的控制方法，包括：在静噪检测器关闭的条件下接收第一信号流; 确定所述第一信号流是否包含在第一工作频率下的突发信号; 如果第一信号流包含突发信号，则打开静噪检测器并且在第二工作频率下由静噪检测器确定第二信号流是否是唤醒信号，其中在接收到第一信号流之后接收第二信号流，以及 第二工作频率大于第一工作频率。 控制方法还包括：如果第二信号流是唤醒信号，则将连接器的操作状态改变为活动状态。 以这种方式，连接器的功耗降低。

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