公开(公告)号：US20240088153A1

公开(公告)日：2024-03-14

申请号：US18513028

申请日：2023-11-17

申请人： Intel Corporation

发明人： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20230006065A1

公开(公告)日：2023-01-05

申请号：US17899429

申请日：2022-08-30

申请人： Intel Corporation

发明人： Gilbert DEWEY ,  Willy RACHMADY ,  Jack T. KAVALIEROS ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Sean T. MA ,  Harold KENNEL ,  Tahir GHANI

IPC分类号： H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

摘要： Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US20200211905A1

公开(公告)日：2020-07-02

申请号：US16236156

申请日：2018-12-28

申请人： Intel Corporation

发明人： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Aaron LILAK ,  Kimin JUN ,  Brennen MUELLER ,  Ehren MANNEBACH ,  Anh PHAN ,  Patrick MORROW ,  Hui Jae YOO ,  Jack T. KAVALIEROS

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/423

摘要： Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230377947A1

公开(公告)日：2023-11-23

申请号：US18356780

申请日：2023-07-21

申请人： Intel Corporation

发明人： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Ehren MANNEBACH ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Hui Jae YOO

IPC分类号： H01L21/762 ,  H01L21/225 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/266

CPC分类号： H01L21/76264 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26533 ,  H01L21/02236 ,  H01L21/02252 ,  H01L29/7853 ,  H01L29/0649 ,  H01L21/31111 ,  H01L21/76267 ,  H01L21/02255 ,  H01L21/266

摘要： Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20220262796A1

公开(公告)日：2022-08-18

申请号：US17731110

申请日：2022-04-27

申请人： Intel Corporation

发明人： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20200312841A1

公开(公告)日：2020-10-01

申请号：US16367175

申请日：2019-03-27

申请人： Intel Corporation

发明人： Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Caleb BARRETT ,  Jay P. GUPTA ,  Nishant GUPTA ,  Kaiwen HSU ,  Byungki JUNG ,  Aravind S. KILLAMPALLI ,  Justin RAILSBACK ,  Supanee SUKRITTANON ,  Prashant WADHWA

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02

摘要： Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

公开(公告)号：US20200287036A1

公开(公告)日：2020-09-10

申请号：US16645758

申请日：2017-12-30

申请人： Intel Corporation

发明人： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC分类号： H01L29/778 ,  H01L29/08 ,  H01L29/205 ,  H01L29/15 ,  H01L21/02 ,  H01L29/66

摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

申请人： Intel Corporation

发明人： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC分类号： H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

摘要： An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20200066843A1

公开(公告)日：2020-02-27

申请号：US16612259

申请日：2017-06-30

申请人： Intel Corporation

发明人： Sean T. MA ,  Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Cheng-Ying HUANG ,  Harold W. KENNEL ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC分类号： H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66

摘要： An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

公开(公告)号：US20240153956A1

公开(公告)日：2024-05-09

申请号：US18409519

申请日：2024-01-10

申请人： Intel Corporation

发明人： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.