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    NON-DATA INCLUSIVE COHERENT (NIC) DIRECTORY FOR CACHE
    2.
    发明申请
    NON-DATA INCLUSIVE COHERENT (NIC) DIRECTORY FOR CACHE 有权
    非数据包含CACHE的内容（NIC）目录

    公开(公告)号：US20140258621A1

    公开(公告)日：2014-09-11

    申请号：US13784958

    申请日：2013-03-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Rebecca M. Gott ,  Pak-Kin Mak ,  Vijayalakshmi Srinivasan ,  Craig R. Walters

    IPC: G06F12/08

    CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0831 ,  G06F2212/283 ,  G06F2212/621

    Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

    Abstract translation: 实施例涉及用于计算机的对称多处理器（SMP）的非数据包含的一致（NIC）目录。 一个方面包括确定SMP的第一处理器节点的多级高速缓存结构中的最高级缓存的第一逐出条目。 另一方面包括确定NIC目录未满。 另一方面包括确定最高级别高速缓存的第一驱逐条目是由多级缓存结构中的较低级别高速缓存所拥有的。 另一方面包括，基于NIC目录不是完整的，并且基于由较低级别高速缓存所拥有的最高级缓存的第一次驱逐条目，将最高级别高速缓存的第一次驱逐条目的地址安装在 NIC目录中的第一个新条目。 另一方面包括使最高级缓存中的第一个逐出条目无效。

    PREINSTALL OF PARTIAL STORE CACHE LINES
    3.
    发明申请
    PREINSTALL OF PARTIAL STORE CACHE LINES 审中-公开

    公开(公告)号：US20180374522A1

    公开(公告)日：2018-12-27

    申请号：US15629923

    申请日：2017-06-22

    Applicant: International Business Machines Corporation

    Inventor： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

    IPC: G11C8/06 ,  G06F3/06 ,  G06F13/16

    Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

    Granting exclusive cache access using locality cache coherency state
    4.
    发明授权
    Granting exclusive cache access using locality cache coherency state 有权

    公开(公告)号：US10572385B2

    公开(公告)日：2020-02-25

    申请号：US15836154

    申请日：2017-12-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Hanno Ulrich

    IPC: G06F12/0815 ,  G06F12/14 ,  G06F12/0813 ,  G06F12/0831

    Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

    Hot cache line arbitration
    5.
    发明授权
    Hot cache line arbitration 有权

    公开(公告)号：US10339064B2

    公开(公告)日：2019-07-02

    申请号：US15472610

    申请日：2017-03-29

    Applicant: International Business Machines Corporation

    Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Jason D. Kohl ,  Pak-Kin Mak ,  Vesselina K. Papazova

    IPC: G06F13/18 ,  G06F12/0877

    Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.

    MEMORY CONTROLLED OPERATIONS UNDER DYNAMIC RELOCATION OF STORAGE
    9.
    发明申请
    MEMORY CONTROLLED OPERATIONS UNDER DYNAMIC RELOCATION OF STORAGE 有权
    存储器动态转移下的内存控制操作

    公开(公告)号：US20160139830A1

    公开(公告)日：2016-05-19

    申请号：US14547639

    申请日：2014-11-19

    Applicant: International Business Machines Corporation

    Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Michael F. Fee ,  Pak-Kin Mak ,  Arthur J. O'Neill ,  Robert J. Sonnelitter, III

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F12/0802 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/283

    Abstract: A computing device is provided and includes a plurality of nodes. Each node includes multiple chips and a node controller at which the multiple chips are assignable to logical partitions. Each of the multiple chips includes processors and a memory unit configured to handle local memory operations originating from the processors. The node controller includes a dynamic memory relocation (DMR) mechanism configured to move data having a DMR storage increment address relative to a local one of the memory units without interrupting a processing of the data by at least one of the logical partitions. During movement of the data by the DMR mechanism, the memory units are disabled from handling the local memory operations matching the DMR storage increment address and the node controller handles the local memory operations matching the DMR storage increment address.

    Abstract translation: 提供了一种计算设备并且包括多个节点。 每个节点包括多个芯片和一个节点控制器，多个芯片可以分配到逻辑分区。 多个芯片中的每一个包括处理器和被配置为处理源自处理器的本地存储器操作的存储器单元。 节点控制器包括动态存储器重定位（DMR）机制，其被配置为移动具有相对于存储器单元中的本地存储器单元的DMR存储增量地址的数据，而不会中断至少一个逻辑分区对数据的处理。 在通过DMR机制移动数据期间，禁止存储器单元处理与DMR存储增量地址匹配的本地存储器操作，并且节点控制器处理与DMR存储器增量地址匹配的本地存储器操作。

    Preinstall of partial store cache lines
    10.
    发明授权
    Preinstall of partial store cache lines 有权

    公开(公告)号：US10529396B2

    公开(公告)日：2020-01-07

    申请号：US15629923

    申请日：2017-06-22

    Applicant: International Business Machines Corporation

    Inventor： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

    IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C8/06

    Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

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