公开(公告)号：US20210334635A1

公开(公告)日：2021-10-28

申请号：US17238490

申请日：2021-04-23

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： In San JEON ,  Chan KIM

IPC: G06N3/063

Abstract: Disclosed is a neural network accelerator including a maximum value determiner outputting a maximum value based on a first magnitude component corresponding to first input data and a second magnitude component corresponding to second input data, a sign determiner outputting a sign component corresponding to the maximum value among a first sign component corresponding to the first input data and a second sign component corresponding to the second input data, as an output sign component, an offset operator quantizing a difference between the first magnitude component and the second magnitude component and outputting an output offset based on the first sign component, the second sign component, and the quantization result, and a magnitude operator calculating an output magnitude component of an output data based on the maximum value and the output offset. Each of the first input data and the second input data is data on a logarithm domain.

公开(公告)号：US20230289582A1

公开(公告)日：2023-09-14

申请号：US18084234

申请日：2022-12-19

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Hwan BAE ,  Jae-Jin LEE ,  Tae Wook KANG ,  Sung Eun KIM ,  Kyung Jin BYUN ,  Kwang IL OH ,  In San JEON

IPC: G06N3/063 ,  G06N3/049

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: A neuron circuit including a first internal circuit that receives a plurality of spike input signals, generates a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and outputs a second sum value by adding a membrane potential value to the first sum value, a spike generating circuit that generates a spike output signal, a membrane potential generating circuit that generates the membrane potential value, a second internal circuit that counts a last spike time based on the spike output signal, and an online learning circuit that receives a last input time from the first internal circuit and performs LTP learning based on the last input time or receives the last spike time from the second internal circuit and performs LTD learning based on the last spike time.

公开(公告)号：US20170149456A1

公开(公告)日：2017-05-25

申请号：US15360925

申请日：2016-11-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： In San JEON ,  Hyuk KIM

IPC: H03M13/29 ,  H04B10/50 ,  H03M13/11 ,  H04L1/00 ,  H03M13/27

CPC classification number: H03M13/2906 ,  H03M13/1102 ,  H03M13/27 ,  H03M13/2927 ,  H03M13/6561 ,  H04B10/50 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0071

Abstract: Provided is an error correction encoder. The error correction encoder includes input nodes for receiving input words, first encoders for generating first parities by performing a first error correction encoding on each of the input words, an interleaver for generating interleaved words by performing interleaving on the input words, a second encoder for generating a plurality of second parities by performing a second error correction encoding on each of the interleaved words, output nodes for outputting each of the input words, first parity output nodes for outputting the first parities, and second parity output nodes for outputting the second parities.

公开(公告)号：US20230306247A1

公开(公告)日：2023-09-28

申请号：US18073830

申请日：2022-12-02

Applicant: Electronics and Telecommunications Research Institute

Inventor： In San JEON ,  Hyuk KIM ,  Jae-Jin LEE ,  Tae Wook KANG ,  Sung Eun KIM ,  Young Hwan BAE ,  Kyung Jin BYUN ,  Kwang IL OH

IPC: G06N3/063 ,  G06N3/049

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: Disclosed is a neuron circuit, which includes a first bias circuit that adds a bias current to an input current to generate a biased input current, a logarithm-based neuron calculation circuit that performs a logarithm calculation on an amount of current of the biased input current to generate an input logarithm value and generates a biased output voltage by performing a logarithm-based Hodgkin-Huxley model calculation based on the input logarithm value, and a second bias circuit that adds a bias voltage to the biased output voltage to generate an output voltage.

公开(公告)号：US20230140256A1

公开(公告)日：2023-05-04

申请号：US17965393

申请日：2022-10-13

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Eun KIM ,  Tae Wook KANG ,  Hyuk KIM ,  Young Hwan BAE ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE ,  In San JEON

IPC: G06N3/063 ,  G06N3/04

Abstract: Disclosed is an electronic device that supports a neural network including a neuron array including neurons, a row address encoder that receives spike signals from neurons and outputs request signals in response to the received spike signals, and a row arbiter tree that receives request signals from the row address encoder and outputs response signals in response to the received request signals. The row arbiter tree includes a first arbiter that arbitrates first and second request signals among request signals, a first latch circuit that stores a state of the first arbiter, a second arbiter that arbitrates third and fourth request signals among request signals, a second latch circuit that stores a state of the second arbiter, and a third arbiter that delivers a response signal to the first and second arbiters based on information stored in the first and second latch circuits.

公开(公告)号：US20220172029A1

公开(公告)日：2022-06-02

申请号：US17536536

申请日：2021-11-29

Applicant: Electronics and Telecommunications Research Institute

Inventor： In San JEON ,  Young-Su KWON ,  Chun-Gi LYUH ,  Young-deuk JEON ,  MIN-HYUNG CHO ,  Jin Ho HAN

IPC: G06N3/04 ,  G06N3/063 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: Disclosed is a simplified sigmoid function circuit which includes a first circuit that performs a computation on input data based on a simplified sigmoid function when a sign of a real region of the input data is positive, a second circuit that performs the computation on the input data based on the simplified sigmoid function when the sign of the real region of the input data is negative, and a first multiplexer that selects and output one of an output of the first circuit and an output of the second circuit, based on the sign of the input data. The simplified sigmoid function is obtained by transforming a sigmoid function of a real region into a sigmoid function of a logarithmic region and performing a variational transformation for the sigmoid function of the logarithmic region.

公开(公告)号：US20250070808A1

公开(公告)日：2025-02-27

申请号：US18663409

申请日：2024-05-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung Eun KIM ,  Tae Wook KANG ,  Hyuk KIM ,  Young Hwan BAE ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE ,  In San JEON

IPC: H04B1/12 ,  H04B1/10 ,  H04B1/16

Abstract: Disclosed is a wake-up circuit including a preprocessing unit that generates a first signal by removing noise from an input signal, a comparison unit that generates a second signal based on the first signal and weight data, an output circuit that generates a power signal based on the second signal and an initialization signal, and a micro control unit (MCU) that generates the initialization signal based on a state signal received from the output circuit. The comparison unit includes a spike neuron network structure that generates the second signal by applying the weight data to the first signal. The output circuit supplies power to an external sensor node in response to the power signal.

公开(公告)号：US20230259745A1

公开(公告)日：2023-08-17

申请号：US17990167

申请日：2022-11-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kwang IL OH ,  Jae-Jin LEE ,  Tae Wook KANG ,  Hyuk KIM ,  In San JEON

IPC: G06N3/04 ,  G06N3/063 ,  G06F7/58

CPC classification number: G06N3/049 ,  G06N3/0472 ,  G06N3/063 ,  G06F7/58

Abstract: Disclosed is a spike neural network circuit including an axon circuit that generates a first input spike signal, a conversion table that converts a first fire probability of a first neuron corresponding to the first input spike signal into a first threshold value, and a probabilistic operator. The probabilistic operator includes a random number generator that generates a random number value based on an event that the first input spike signal is at a first logic level, a random number comparator that generates a first comparison signal by comparing the first threshold value with the random number value, and a spike generator that generates an output spike signal corresponding to the first neuron based on an event that the first comparison signal is at the first logic level.

公开(公告)号：US20230068675A1

公开(公告)日：2023-03-02

申请号：US17895532

申请日：2022-08-25

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Eun KIM ,  Tae Wook KANG ,  Hyuk KIM ,  Young Hwan BAE ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE ,  In San JEON

IPC: G06N3/063 ,  G06N3/04

Abstract: Disclosed is an encoder including event layer outputs first and second event signals, weight layer applies first and second weights to the first and second event signals respectively, and provides the first event signal in which the first weight is applied and the second event signal in which the second weight is applied to first node, and first spike generation circuit generates first input spike signal of which firing period is changed based on voltage level of the first node. The voltage level of the first node is reduced continuously, increases for first voltage corresponding to the first weight in response to the first event signal activated, and increases for second voltage corresponding to the second weight in response to the second event signal activated.

公开(公告)号：US20240112002A1

公开(公告)日：2024-04-04

申请号：US18344275

申请日：2023-06-29

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Eun KIM ,  Tae Wook KANG ,  Hyuk KIM ,  Young Hwan BAE ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE ,  In San JEON

IPC: G06N3/049 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063

Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.