公开(公告)号：US08984380B2

公开(公告)日：2015-03-17

申请号：US13733798

申请日：2013-01-03

Applicant: ALTERA Corporation

Inventor： Divya Vijayaraghavan ,  Chong H. Lee ,  Keith Duwel ,  Vinson Chan

IPC: H03M13/00 ,  H03M13/35 ,  H03M13/37 ,  H04L12/931 ,  H03M13/07

CPC classification number: H03M13/353 ,  H03M13/07 ,  H03M13/3738 ,  H03M13/63 ,  H03M13/6511 ,  H03M13/6516 ,  H03M13/6519 ,  H04L49/604

Abstract: A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Abstract translation: 一种用于操作可配置为在单个设备上支持一个或多个通信标准的通信电路的方法和系统。 通信电路包括：发送装置，其包括以第一数据速率操作的PCS模块和以第二数据速率操作的第二PCS模块。 电路还包括多个前向纠错（FEC）编码和解码模块，每个以指定的数据速率运行。 第一组FEC编码和解码模块被配置为支持第一PCS模块，并且第二组FEC编码和解码模块被配置为支持第二PCS模块。

公开(公告)号：US20140189459A1

公开(公告)日：2014-07-03

申请号：US13733798

申请日：2013-01-03

Applicant: ALTERA Corporation

Inventor： Divya Vijayaraghavan ,  Chong H. Lee ,  Keith Duwel ,  Vinson Chan

IPC: H03M13/29

CPC classification number: H03M13/353 ,  H03M13/07 ,  H03M13/3738 ,  H03M13/63 ,  H03M13/6511 ,  H03M13/6516 ,  H03M13/6519 ,  H04L49/604

Abstract: A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Abstract translation: 一种用于操作可配置为在单个设备上支持一个或多个通信标准的通信电路的方法和系统。 通信电路包括：发送装置，其包括以第一数据速率操作的PCS模块和以第二数据速率操作的第二PCS模块。 电路还包括多个前向纠错（FEC）编码和解码模块，每个以指定的数据速率运行。 第一组FEC编码和解码模块被配置为支持第一PCS模块，并且第二组FEC编码和解码模块被配置为支持第二PCS模块。

公开(公告)号：US10404627B2

公开(公告)日：2019-09-03

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

公开(公告)号：US09042404B2

公开(公告)日：2015-05-26

申请号：US13925284

申请日：2013-06-24

Applicant: ALTERA CORPORATION

Inventor： Keith Duwel ,  Michael Menghui Zheng ,  Vinson Chan ,  Kalyan Kankipati

IPC: H04J3/16 ,  H04J3/04 ,  H04L5/22 ,  H04J3/06

CPC classification number: H04J3/1682 ,  H04J3/04 ,  H04J3/0685 ,  H04L5/22 ,  H04Q2213/13208 ,  H04Q2213/13322

Abstract: The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

Abstract translation: 本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。 公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。 根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。 这有利地允许优化用于两种类型的通道结合的配置。 在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。 这种去耦有利地消除了先前架构的刚性约束。

公开(公告)号：US10216219B1

公开(公告)日：2019-02-26

申请号：US15356052

申请日：2016-11-18

Applicant: Altera Corporation

Inventor： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee ,  Vinson Chan

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/08

Abstract: A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. Configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations.

公开(公告)号：US20180034748A1

公开(公告)日：2018-02-01

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

CPC classification number: H04L49/90 ,  H04L47/6245

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.