公开(公告)号：US08928063B2

公开(公告)日：2015-01-06

申请号：US13618182

申请日：2012-09-14

申请人： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

发明人： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

IPC分类号： H01L29/792 ,  H01L21/20

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

摘要翻译： 非易失性存储器件包括从衬底垂直延伸的沟道层，沿着沟道层交替层叠的多个层间电介质层和多个栅极电极，以及插入在沟道层和每个沟道层之间的气隙 的多个栅电极。 非易失性存储器件可以通过用插入位于栅电极和具有气隙的电荷存储层之间的电荷阻挡层来抑制电子的反向隧道而提高擦除操作特性，以及制造非易失性存储器件的方法。

公开(公告)号：US08872254B2

公开(公告)日：2014-10-28

申请号：US13598414

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/66833

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.

摘要翻译： 半导体器件包括交替堆叠的字线和层间绝缘层，穿透字线和层间绝缘层的沟道层，围绕沟道层的隧道绝缘层和围绕隧道绝缘层的第一电荷陷阱层，插入在字 线路和隧道绝缘层，并掺杂有第一杂质。

公开(公告)号：US20130320424A1

公开(公告)日：2013-12-05

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，第二源极层基本上形成在第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20130207178A1

公开(公告)日：2013-08-15

申请号：US13603339

申请日：2012-09-04

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/32133 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

公开(公告)号：US08288819B2

公开(公告)日：2012-10-16

申请号：US12953255

申请日：2010-11-23

申请人： Yong Soo Kim ,  Hong Seon Yang ,  Se Aug Jang ,  Seung Ho Pyi ,  Kwon Hong ,  Heung Jae Cho ,  Kwan Yong Lim ,  Min Gyu Sung ,  Seung Ryong Lee ,  Tae Yoon Kim

发明人： Yong Soo Kim ,  Hong Seon Yang ,  Se Aug Jang ,  Seung Ho Pyi ,  Kwon Hong ,  Heung Jae Cho ,  Kwan Yong Lim ,  Min Gyu Sung ,  Seung Ryong Lee ,  Tae Yoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L27/10876 ,  H01L29/518 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

摘要翻译： 一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。 栅极导电层填充灯泡型凹陷区域。 栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

公开(公告)号：US07981786B2

公开(公告)日：2011-07-19

申请号：US11966231

申请日：2007-12-28

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  Y10S438/942

摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.

摘要翻译： 一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案 使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层 用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及 对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理 作为过量蚀刻以将电荷捕获层除去指定的厚度。

公开(公告)号：US20100181599A1

公开(公告)日：2010-07-22

申请号：US12749176

申请日：2010-03-29

申请人： Yong-Soo KIM ,  Hong-Seon YANG ,  Seung-Ho PYI ,  Tae-Hang AHN

发明人： Yong-Soo KIM ,  Hong-Seon YANG ,  Seung-Ho PYI ,  Tae-Hang AHN

IPC分类号： H01L29/78 ,  H01L27/12

CPC分类号： H01L29/0847 ,  H01L21/18 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer

摘要翻译： 半导体器件包括衬底，形成在衬底上的栅极，设置在栅极的第一和第二侧壁上的栅极间隔，以及形成在靠近栅极间隔物的衬底中的源/漏区。 源极/漏极区包括包括Ge的第一和第二外延层，其中形成在第一外延层和衬底之间的界面层上的第二外延层具有比第一外延层更高的锗浓度

公开(公告)号：US20090278225A1

公开(公告)日：2009-11-12

申请号：US12504427

申请日：2009-07-16

申请人： Seung-Ho Pyi

发明人： Seung-Ho Pyi

IPC分类号： H01L29/06

CPC分类号： H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

摘要翻译： 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。

公开(公告)号：US20090163014A1

公开(公告)日：2009-06-25

申请号：US12139623

申请日：2008-06-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/31616

摘要： A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

摘要翻译： 一种用于制造具有电荷捕获层的非易失性存储器件的方法，其中在半导体衬底上形成有隧道层，电荷俘获层，阻挡层和控制栅电极。 通过向控制栅电极施加磁场来增加控制栅电极的温度。 通过允许将升高的温度转移到与控制栅电极接触的阻挡层而使阻挡层致密化。

公开(公告)号：US20080157185A1

公开(公告)日：2008-07-03

申请号：US11770985

申请日：2007-06-29

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Yong Soo Kim

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Yong Soo Kim

IPC分类号： H01L29/792 ,  H01L21/3205

CPC分类号： H01L21/28282

摘要： A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.

摘要翻译： 非易失性存储器件包括衬底，衬底上的隧道层，在隧穿层上方包括氮化物层和氮化硼氮化物层的电荷俘获层，以及电荷俘获层上的阻挡层，以及控制栅极 电极布置在阻挡层上。