公开(公告)号：US12126362B2

公开(公告)日：2024-10-22

申请号：US18029328

申请日：2021-09-28

申请人： NTT Research, Inc.

发明人： Ofer Grossman ,  Justin Holmgren ,  Eylon Yogev

IPC分类号： H03M13/19 ,  H04L9/40

CPC分类号： H03M13/19 ,  H04L63/0428

摘要： The invention relates to systems, methods, network devices, and machine-readable media for encoding an input message with robustness against noise by executing a compressing hash function on the input message, encoding an output of the hash function and the input message to generate a single combined message, executing a permutation function on the combined message, and encoding the result of the permutation function with a list-decodable code.

公开(公告)号：US12113550B1

公开(公告)日：2024-10-08

申请号：US18331499

申请日：2023-06-08

申请人： NXP B.V.

发明人： Björn Fay

IPC分类号： H03M13/19 ,  G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC分类号： H03M13/19 ,  G06F11/1012 ,  G06F11/1076 ,  H03M13/09

摘要： A method for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error correcting code (ECC) as first encoded data, wherein the ECC is configured to have a minimum Hamming distance of at least 4t+1 in order to correct up to t bit errors and detect up to 3t bit errors where t≥1; determining a Hamming weight of the first encoded data; encoding the determined Hamming weight, wherein for all higher Hamming weights the encoding should have at least 2t+1 bit-positions that change from 1 to 0 per Hamming weight; concatenating the first encoded data and the encoded Hamming weight as concatenated data; and storing the concatenated data in the memory.

公开(公告)号：US12081234B2

公开(公告)日：2024-09-03

申请号：US17874212

申请日：2022-07-26

申请人： Intel Corporation

发明人： Kjersten E. Criss

IPC分类号： H03M13/11 ,  H03M13/00 ,  H03M13/19 ,  H03M13/29

CPC分类号： H03M13/1105 ,  H03M13/19 ,  H03M13/2942 ,  H03M13/617 ,  H03M13/00 ,  H03M13/11 ,  H03M13/29

摘要： An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

公开(公告)号：US11996157B2

公开(公告)日：2024-05-28

申请号：US17375622

申请日：2021-07-14

申请人： SK hynix Inc.

发明人： Choung Ki Song

IPC分类号： G11C29/42 ,  G06F7/544 ,  G06F17/16 ,  G06N3/063 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19

CPC分类号： G11C29/42 ,  G06F7/5443 ,  G06F17/16 ,  G06N3/063 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/19

摘要： A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.

公开(公告)号：US20240162919A1

公开(公告)日：2024-05-16

申请号：US18414909

申请日：2024-01-17

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Yutaka MURAKAMI ,  Tomohiro Kimura ,  Mikihiro Ouchi

IPC分类号： H03M13/25 ,  H03M13/00 ,  H03M13/11 ,  H03M13/19 ,  H03M13/35 ,  H04L1/00

CPC分类号： H03M13/255 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/19 ,  H03M13/35 ,  H03M13/6362 ,  H04L1/00

摘要： One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.

公开(公告)号：US11953988B2

公开(公告)日：2024-04-09

申请号：US16858281

申请日：2020-04-24

申请人： Micron Technology, Inc.

发明人： Scott E Schaefer ,  Aaron P. Boehm

IPC分类号： G06F11/10 ,  G11C11/22 ,  H03M13/45 ,  G06F3/06 ,  G06F11/20 ,  G06F13/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/00 ,  H03M13/19

CPC分类号： G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H03M13/458 ,  G06F3/0659 ,  G06F11/1052 ,  G06F11/201 ,  G06F13/00 ,  G11C7/1006 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/19 ,  H03M13/6561

摘要： Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

公开(公告)号：US11929763B2

公开(公告)日：2024-03-12

申请号：US17216407

申请日：2021-03-29

申请人： Westhold Corporation

发明人： Shu Lin ,  Khaled Ahmed Sabry Abdel-Ghaffar ,  Juane Li ,  Keke Liu

IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/27 ,  H03M13/29 ,  H03M13/13 ,  H03M13/19

CPC分类号： H03M13/116 ,  G06F11/10 ,  H03M13/036 ,  H03M13/1174 ,  H03M13/1515 ,  H03M13/158 ,  H03M13/2757 ,  H03M13/2906 ,  H03M13/611 ,  H03M13/136 ,  H03M13/152 ,  H03M13/19

摘要： Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols.

公开(公告)号：US11611358B2

公开(公告)日：2023-03-21

申请号：US16816093

申请日：2020-03-11

申请人： Kioxia Corporation

发明人： David M. Symons

IPC分类号： H03M13/19 ,  H03M13/15 ,  H03M13/23 ,  H03M13/17

摘要： Various implementations described herein relate to correcting errors in Dynamic Random Access Memory (DRAM). A memory controller uses an Error Correcting Code (ECC) to store an encoded data word within a DRAM die. The DRAM die is communicatively coupled the memory controller by a memory data bus. The DRAM die includes on-die error correction for data bits stored in the DRAM. Upon reading the encoded data word, the memory controller corrects and detects one or more errors. The one or more errors are introduced by at least one of the on-die error correction of the DRAM die or the memory data bus.

公开(公告)号：US11579953B2

公开(公告)日：2023-02-14

申请号：US17856661

申请日：2022-07-01

申请人： Fort Robotics, Inc.

发明人： Kerfegar Khurshed Katrak ,  Nathan Bivans

IPC分类号： G06F11/07 ,  H03M13/15 ,  H03M13/19 ,  G06F11/00

摘要： A method includes, storing a set of valid codewords including: a first valid functional codeword representing a functional state of a controller subsystem; a first valid fault codeword representing a fault state of the controller subsystem and characterized by a minimum hamming distance from the first valid functional codeword; a second valid functional codeword representing a functional state of a controller; and a second valid fault codeword representing a fault state of the controller; in response to detecting functional operation of the controller subsystem, storing the first valid functional codeword in a first memory; in response to detecting a match between contents of the first memory and the first valid functional codeword, outputting the second valid functional codeword; in response to detecting a mismatch between contents of the first memory and every codeword in the first set of valid codewords, outputting the second valid fault codeword.

公开(公告)号：US20220407540A1

公开(公告)日：2022-12-22

申请号：US17895466

申请日：2022-08-25

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Yi LI ,  Jiancong LI ,  Xiangshui MIAO ,  Peng YAN ,  Guiyou PU ,  Xiaozhong SHI ,  Keji HUANG

IPC分类号： H03M13/19 ,  H03M13/00

摘要： The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.