公开(公告)号：US5229660A

公开(公告)日：1993-07-20

申请号：US644780

申请日：1991-01-23

申请人： Shinichi Shiotsu ,  Masahiro Tanaka

发明人： Shinichi Shiotsu ,  Masahiro Tanaka

IPC分类号： H03K19/003 ,  H03K19/088

CPC分类号： H03K19/00307

摘要： An integrated circuit comprising a logic output circuit (10) having a resisting voltage condition which is a predetermined voltage lower than a low voltage level in an output terminal of the logic output circuit, conducting unit (11) connected to the output terminal of the logic output circuit for conducting when voltage exceeding the resisting voltage condition of the logic output circuit is applied to the output terminal, trigger-voltage generating unit (12) connected to the conducting unit for generating a trigger voltage when the conducting unit conducts, and control unit (13) provided between the trigger-voltage generating unit and the logic output circuit to turn off the logic output circuit in response to the trigger voltage from the trigger-voltage generating unit.

摘要翻译： 一种集成电路，包括在逻辑输出电路的输出端子中具有低于低电压电平的预定电压的电阻状态的逻辑输出电路（10），与逻辑输出电路的输出端连接的导通单元（11） 输出电路，当超过逻辑输出电路的阻抗电压条件的电压被施加到输出端子时，连接到导电单元的触发电压产生单元（12），用于当导电单元导通时产生触发电压;以及控制单元 （13），其设置在触发电压产生单元和逻辑输出电路之间，以响应于来自触发电压产生单元的触发电压来关闭逻辑输出电路。

公开(公告)号：US5204550A

公开(公告)日：1993-04-20

申请号：US823225

申请日：1992-01-21

申请人： Horst Jungert

发明人： Horst Jungert

IPC分类号： H03K17/04 ,  H03K17/042 ,  H03K17/567 ,  H03K17/66 ,  H03K19/0175 ,  H03K19/088 ,  H04L25/02

CPC分类号： H03K17/04213 ,  H03K17/666

摘要： An output stage for a digital circuit for emitting a signal with the one or the other binary value in dependence upon an input signal includes an output transistor at the collector of which the signal to be emitted can be tapped off and to the base of which a current dependent on the input signal is supplied. In the line leading to the base of the output transistor, a device is disposed for setting the base current in dependence upon the current flowing through the collector-emitter path of the output transistor.

公开(公告)号：US5132566A

公开(公告)日：1992-07-21

申请号：US557990

申请日：1990-07-25

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K19/003 ,  H03K17/081 ,  H03K19/088

CPC分类号： H03K17/08112

摘要： An output circuit capable of limiting an output current from a BiMOS semiconductor integrated circuit without adversely affecting an operational speed includes a plurality of bipolar transistors connected to form a Darlington circuit and at least one field effect transistor which can be either a P-channel or an N-channel transistor. The circuit is capable of removing rise current limitations of the bipolar transistors in the Darlington circuit during a normal operation by using a single MOS transistor to provide a branch circuit for the Darlington circuit, which limits the output current of the circuit under the specific condition that it provides a high level output and its output terminal is short-circuited to the ground.

摘要翻译： 能够限制来自BiMOS半导体集成电路的输出电流而不会不利地影响操作速度的输出电路包括连接形成达林顿电路的多个双极晶体管和至少一个场效应晶体管，其可以是P沟道或 N沟道晶体管。 该电路能够在正常操作期间消除达林顿电路中的双极晶体管的上升电流限制，通过使用单个MOS晶体管为达林顿电路提供分支电路，这限制了在特定条件下电路的输出电流， 它提供高电平输出，其输出端短路到地。

公开(公告)号：US5051623A

公开(公告)日：1991-09-24

申请号：US537903

申请日：1990-06-16

申请人： Roy L. Yarbrough ,  Julio R. Estrada

发明人： Roy L. Yarbrough ,  Julio R. Estrada

IPC分类号： H03K17/04 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/082 ,  H03K19/088

CPC分类号： H03K19/013 ,  H03K19/0826

摘要： The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver. The emitter follower DCMK signal output and voltage divider coupling reduce DCMK signal generation delay, eliminate current hogging between Miller killer transistor elements of the multiple output buffers of a multi-bit output, and dispense with the ballast resistors which introduce delay.

摘要翻译： 用于TTL三态输出缓冲器电路的较低输出下拉三态电路包括具有＆amp; O和O信号输入的使能信号反相器缓冲器和提供输出使能OE信号的OE信号输出，以及具有耦合在 TTL三态输出下拉晶体管的基极节点和低电位电源轨。 发射极跟随器晶体管元件的基极节点连接到＆Upbar＆O信号输入端，发射极节点提供与上拉和O信号输入同相的DC Miller杀手DCMK信号输出。 分压器将DCMK信号输出端耦合到Miller抑制晶体管元件的基极节点，用于在输出端的高阻抗三态期间响应于高电位DCMK信号而放电输出下拉晶体管的基极。 DC Miller杀手电路应用于高速TTL三态输出和多位线驱动器。 射极跟随器DCMK信号输出和分压器耦合降低了DCMK信号产生延迟，消除了多位输出的多输出缓冲器的米勒杀伤晶体管元件之间的电流占空比，并且省去了引入延迟的镇流电阻。

公开(公告)号：US4972104A

公开(公告)日：1990-11-20

申请号：US202971

申请日：1988-06-03

申请人： Julio R. Estrada

发明人： Julio R. Estrada

IPC分类号： H03K17/16 ,  H03K17/66 ,  H03K19/00 ,  H03K19/018 ,  H03K19/088

CPC分类号： H03K19/088 ,  H03K19/001

摘要： An anti-simultaneous conduction transistor is incorporated into the standard TTL circuit totem pole to reduce simultaneous conduction of the pullup and pulldown transistor elements of the totem pole. The collector of the active discharge anti-simultaneous conduction transistor element (Q5) is operatively coupled to a base of the pullup transistor element (Q2,Q3) through a diode (D5), the emitter is coupled to low potential, and the base is coupled to the base of the pulldown transistor element (Q4) through ballast resistance (R6,R7). The anti-simultaneous conduction transistor element (Q5) mirrors the conducting state of the pulldown transistor element (Q4) without current hogging substantially diverting or discharging base current from the base of the pullup transistor element (Q2,Q3) whenever the pulldown transistor element (Q4) is conducting. Undesirable current spikes in the sourcing current are avoided by preventing simultaneous conduction in the totem pole.

公开(公告)号：US4950927A

公开(公告)日：1990-08-21

申请号：US403062

申请日：1989-09-05

申请人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

发明人： Gerard Boudon ,  Armand Brunin ,  Bernard Denis ,  Pierre Mollier ,  Philippe Stoppa

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/06 ,  H03K19/003 ,  H03K19/082 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/084 ,  H03K19/088

摘要： A DTT type basic logic circuit exhibiting improved immunity to noise and including input diodes for receiving input signals A, B, . . .; an input transistor the emitter of which receives an additional input signal X and the base of which is connected to the anodes of the input diodes; and an output inverter transistor disposed so that the signal at the output thereof represents the logic function X(AB . . .). From this circuit, a family of logic circuits suitable for realizing very-large-scale-integration logic networks in a master slice can be developed. The master slice comprises general-purpose cells in which pre-diffused semiconductor elements can be interconnected to form the desired circuits.

摘要翻译： 具有改进的抗噪声能力的DTT型基本逻辑电路，包括用于接收输入信号A，B的输入二极管。 。 。 输入晶体管，其发射极接收附加的输入信号X，其基极连接到输入二极管的阳极; 以及输出反相晶体管，其输出端的信号表示逻辑功能＆upbar＆X（AB ...）。 从该电路可以开发适合在主片中实现大规模集成逻辑网络的逻辑电路系列。 主切片包括通用单元，其中预扩散半导体元件可以互连以形成期望的电路。

公开(公告)号：US4890051A

公开(公告)日：1989-12-26

申请号：US289731

申请日：1988-12-27

申请人： Byung-Youn Kim ,  Yong-Bo Park ,  Tae-Sung Jung

发明人： Byung-Youn Kim ,  Yong-Bo Park ,  Tae-Sung Jung

IPC分类号： H03K19/088 ,  G05F3/24 ,  G11C11/409 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/01855 ,  G05F3/247

摘要： A CMOS input buffer for converting the TTL level signals to the CMOS level signals, thereby being capable of stably operating within all allowable range of the power supply voltage, is disclosed. Said CMOS input buffer includes an inverter, a reference voltage generating circuit, a power supply voltage tracer circuit and an input circuit. The input circuit includes P-channel MOS transistors and N-channel MOS transistors so as to supply a stable logic output in response to the input signal of TTL level, regardless of variation of the power supply voltage Vcc, under the control of a voltage that is approximately proportional to the difference between the reference voltage and the power supply voltage within a fixed range of the power supply voltage.

摘要翻译： 公开了用于将TTL电平信号转换为CMOS电平信号的CMOS输入缓冲器，从而能够在电源电压的所有容许范围内稳定地工作。 所述CMOS输入缓冲器包括反相器，参考电压产生电路，电源电压示踪器电路和输入电路。 输入电路包括P沟道MOS晶体管和N沟道MOS晶体管，以便响应于TTL电平的输入信号而提供稳定的逻辑输出，而不管电源电压Vcc的变化，在电压 大致与电源电压的固定范围内的参考电压和电源电压之间的差成比例。

公开(公告)号：US4868424A

公开(公告)日：1989-09-19

申请号：US124971

申请日：1987-11-24

申请人： Robert J. Bosnyak ,  Jeff Huard

发明人： Robert J. Bosnyak ,  Jeff Huard

IPC分类号： H03K19/088 ,  H03K17/615 ,  H03K19/00 ,  H03K19/013

CPC分类号： H03K19/001 ,  H03K19/0136

摘要： A circuit which provides additional drive current during substantially the entire transition of an output signal from a logical one to a logical zero state, thereby causing the pulldown transistor in the TTL output stage to rapidly turn on, providing increased switching speed between logical one and logical zero output state for a given power consumption. Alternatively, for a given switching speed, power consumption is reduced.

公开(公告)号：US4841172A

公开(公告)日：1989-06-20

申请号：US225495

申请日：1988-07-28

申请人： Masaji Ueno ,  Hideaki Masuoka

发明人： Masaji Ueno ,  Hideaki Masuoka

IPC分类号： H03K17/04 ,  H03K17/66 ,  H03K19/00 ,  H03K19/013 ,  H03K19/017 ,  H03K19/08 ,  H03K19/088

CPC分类号： H03K19/0136 ,  H03K19/0013 ,  H03K19/01721

摘要： A logic circuit comprises a current control means including first and second MOS transistors for controlling the current to the output circuit and also for controlling the output wave form, in accordance with the input signal and the output signal. When the output signal rises from a low level to a high level, a large current is supplied to the output circuit to get a steep rise. When the output signal is high level, the current to the output circuit becomes small, and the power consumption is reduced.

公开(公告)号：US4800294A

公开(公告)日：1989-01-24

申请号：US147484

申请日：1988-01-25

申请人： Keith A. Taylor

发明人： Keith A. Taylor

IPC分类号： H03K19/088 ,  G01R31/319 ,  H03K5/02 ,  H03K17/66 ,  H03K19/0175 ,  H03K19/082 ,  H03K3/023 ,  H03K5/12

CPC分类号： G01R31/31924 ,  H03K17/666 ,  H03K19/0826 ,  G01R31/31922

摘要： A pin driver circuit for driving a digital integrated circuit is capable of producing symmetrical rise and fall characteristics, yet is suitable for implementation in monolithic bipolar integrated circuits. This circuit includes a pair of matched transconductance amplifiers, one at each end of an output resistor, connected between a voltage source and a return voltage. Each amplifier has one of a pair of equal resistors between its input terminal and high output terminal to develop an equal swing voltage on alternate ends of the output resistor when a swing voltage current source is switched between the two input resistors by a control signal. The output is taken from the junction between the output resistor and the low output terminal of the amplifier at the high end of the output resistor. An additional current source is connected to the input resistor of the amplifier at the low end of the divider to provide a current which may be adjusted to allow the standing current in the output resistor to be reduced to a satisfactory minimum. Additional circuitry can be added to allow the output to be put in a high impedance condition. In a preferred embodiment, the high level of the output, the swing voltage, and the standing current may all be controlled.

摘要翻译： 用于驱动数字集成电路的引脚驱动电路能够产生对称的上升和下降特性，但适用于单片双极集成电路中的实现。 该电路包括一对匹配的跨导放大器，一个在输出电阻器的每一端，连接在电压源和返回电压之间。 每个放大器在其输入端和高输出端之间具有一对相等电阻中的一个，当通过控制信号在两个输入电阻之间切换摆动电压电流源时，在输出电阻的交替端产生相等的摆幅电压。 输出取自输出电阻器高端的放大器的输出电阻和低输出端之间的结。 额外的电流源连接到放大器的输入电阻器在分压器的低端，以提供可以被调节的电流，以使输出电阻器中的驻极电流能够降低到令人满意的最小值。 可以添加额外的电路，以使输出处于高阻抗状态。 在优选实施例中，可以全部控制输出的高电平，摆幅电压和静止电流。