公开(公告)号：US4868424A

公开(公告)日：1989-09-19

申请号：US124971

申请日：1987-11-24

申请人： Robert J. Bosnyak ,  Jeff Huard

发明人： Robert J. Bosnyak ,  Jeff Huard

IPC分类号： H03K19/088 ,  H03K17/615 ,  H03K19/00 ,  H03K19/013

CPC分类号： H03K19/001 ,  H03K19/0136

摘要： A circuit which provides additional drive current during substantially the entire transition of an output signal from a logical one to a logical zero state, thereby causing the pulldown transistor in the TTL output stage to rapidly turn on, providing increased switching speed between logical one and logical zero output state for a given power consumption. Alternatively, for a given switching speed, power consumption is reduced.

公开(公告)号：US07541611B2

公开(公告)日：2009-06-02

申请号：US11339003

申请日：2006-01-24

申请人： Thomas G. O'Neill ,  Robert J. Bosnyak

发明人： Thomas G. O'Neill ,  Robert J. Bosnyak

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L29/4238

摘要： A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan current flow. A system is also described, including the previously described device and a second transistor. The pathway for the flow of the majority of the current carriers in the device defines a first direction. The second transistor also has at least two terminals, and a pathway for a majority of current carriers between the two terminals defines a second direction. The angle between the first direction and the second direction is nonzero and acute.

摘要翻译： 描述了一种装置，包括具有第一端子的第一扩散区域，具有第二端子的第二扩散区域和设置在第一扩散区域和第二扩散区域之间的沟道区域。 此外，第一端子和第二端子被偏移以使得不是曼哈顿电流。 还描述了一种系统，包括先前描述的器件和第二晶体管。 用于装置中大多数当前载体的流动的路径限定第一方向。 第二晶体管还具有至少两个端子，并且用于两个端子之间的大多数电流载流子的通路限定第二方向。 第一方向和第二方向之间的角度是非零和锐角。

公开(公告)号：US07129774B1

公开(公告)日：2006-10-31

申请号：US11126585

申请日：2005-05-11

申请人： Robert J. Bosnyak

发明人： Robert J. Bosnyak

IPC分类号： G05F3/02

CPC分类号： G05F3/30 ,  G11C5/145 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A method and apparatus for generating a reference signal involves (i) generating a CTAT voltage and a PTAT voltage, (ii) generating a first digital signal and a second digital signal having an amplified difference dependent on a difference between the CTAT voltage and the PTAT voltage, and (iii) dependent on the first digital signal and the second digital signal, adding or subtracting charge from the reference signal, where the reference signals controls the conductivity of devices that drive current through the devices that are used to generate the CTAT and PTAT voltages.

摘要翻译： 用于产生参考信号的方法和装置包括（i）产生CTAT电压和PTAT电压，（ii）根据CTAT电压和PTAT之间的差产生具有放大差分的第一数字信号和第二数字信号 电压，以及（iii）取决于第一数字信号和第二数字信号，从参考信号中增加或减去电荷，其中参考信号控制驱动电流通过用于产生CTAT的装置的电流的电导率，以及 PTAT电压。

公开(公告)号：US06738415B2

公开(公告)日：2004-05-18

申请号：US09815358

申请日：2001-03-22

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H04B138

CPC分类号： H04L5/14 ,  H04L25/085 ,  H04L27/367

摘要： A bi-directional communication system and transceiver configuration are described, which employ a bi-directional reference to account for both common-mode and differential noise introduced at either end of a bi-directional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.

摘要翻译： 描述了双向通信系统和收发器配置，其采用双向参考来考虑在双向通信信道的任一端引入的共模和差分噪声。 一些实现利用了双向芯片到芯片通信方案中描述的技术。 在一些实现中，本文所述的双向参考技术的优点是获得的，同时采用发射信号的预失真来补偿通信信道中的符号间干扰（ISI）。

公开(公告)号：US06414538B1

公开(公告)日：2002-07-02

申请号：US09680673

申请日：2000-10-06

申请人： Robert J. Bosnyak ,  Jose M. Cruz

发明人： Robert J. Bosnyak ,  Jose M. Cruz

IPC分类号： G05F302

CPC分类号： G05F3/205

摘要： A low-pass filter to filter the internal bias voltages. It is connected locally at the bias voltage input of each bias current source the low-pass filter reduces the AC overshoot oscillations of a local bias voltage generated by the bias voltage generator upon a changing in the amount of current sourced by other current sources. A single bias voltage generator is connected to a bias voltage input of a number of bias current sources. Each current source has a low pass filter to filter the bias voltage.

摘要翻译： 低通滤波器来滤除内部偏置电压。 它在每个偏置电流源的偏置电压输入端局部连接，低通滤波器减少由偏置电压发生器产生的局部偏置电压的交流过冲振荡，这是由于其他电流源的电流量的变化。 单个偏置电压发生器连接到多个偏置电流源的偏置电压输入端。 每个电流源都有一个低通滤波器来滤除偏置电压。

公开(公告)号：US06396316B1

公开(公告)日：2002-05-28

申请号：US09667060

申请日：2000-09-21

申请人： Jose M. Cruz ,  Robert J. Bosnyak

发明人： Jose M. Cruz ,  Robert J. Bosnyak

IPC分类号： H03B100

CPC分类号： H03K19/00353 ,  H03K5/145

摘要： A clock buffer circuit utilizing an LC circuit for jitter reduction. The circuit includes a differential amplifier that is coupled to a buffer stage. The output of the buffer circuit comprises the buffer stage output. An inductor and capacitor are coupled between the buffer stage output and ground. The values of the inductor and capacitor are specified such that the resonant frequency of the LC circuit corresponds to the nominal clock frequency. The entire buffer circuit including the capacitor and inductor may be fabricated on an integrated circuit. Alternatively the capacitor and/or inductor may comprise discrete components that are coupled to the buffer stage output. Additionally, multiple capacitors and/or inductors may be fabricated on the integrated circuit to permit the resonant frequency of the LC circuit to be adjusted to match the nominal clock frequency. The capacitor(s) and/or inductor(s) on the integrated circuit may be connected to integrated circuit contacts and coupled to the buffer stage output via external connections or alternatively, via semiconductor switches.

摘要翻译： 使用LC电路的抖动降低的时钟缓冲电路。 电路包括耦合到缓冲器级的差分放大器。 缓冲电路的输出包括缓冲器级输出。 电感和电容耦合在缓冲级输出和地之间。 规定电感器和电容器的值，使得LC电路的谐振频率对应于标称时钟频率。 包括电容器和电感器的整个缓冲电路可以在集成电路上制造。 或者，电容器和/或电感器可以包括耦合到缓冲器级输出的分立元件。 此外，可以在集成电路上制造多个电容器和/或电感器，以允许调整LC电路的谐振频率以匹配标称时钟频率。 集成电路上的电容器和/或电感器可以连接到集成电路触点，并通过外部连接或通过半导体开关耦合到缓冲器级输出端。

公开(公告)号：US06384642B1

公开(公告)日：2002-05-07

申请号：US09680572

申请日：2000-10-06

申请人： Robert J. Bosnyak ,  José M. Cruz ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  José M. Cruz ,  Robert J. Drost

IPC分类号： H03B100

CPC分类号： H04L25/0292 ,  H04L25/0278

摘要： In an input receiver circuit includes a signal input for receiving a signal input to a chip, a chip output for supplying a buffered signal to circuitry on the chip and a positive feedback circuit coupled between the chip output and the signal input. The positive feedback circuit might comprise a first inverter having an input coupled to the signal input, a second inverter having an input coupled to an output of the first inverter, wherein an output of the second inverter provides the chip output, and an inverting buffer having an input coupled to the output of the second inverter and an output coupled to the signal input.

摘要翻译： 在输入接收机电路中包括用于接收输入到芯片的信号的信号输入端，用于将缓冲信号提供给芯片上的电路的芯片输出端以及耦合在芯片输出和信号输入端之间的正反馈电路。 正反馈电路可以包括具有耦合到信号输入的输入的第一反相器，具有耦合到第一反相器的输出的输入的第二反相器，其中第二反相器的输出提供芯片输出，反相缓冲器具有 耦合到第二反相器的输出的输入端和耦合到信号输入的输出。

公开(公告)号：US6031406A

公开(公告)日：2000-02-29

申请号：US883524

申请日：1997-06-26

申请人： Robert J. Drost ,  Robert J. Bosnyak ,  Jose M. Cruz

发明人： Robert J. Drost ,  Robert J. Bosnyak ,  Jose M. Cruz

IPC分类号： H01L27/02 ,  H03K5/00

CPC分类号： H01L27/0207

摘要： An apparatus for suppressing the effect of noise from a first circuit on the performance of a second circuit wherein the first and second circuits are on a common substrate. Each of the first and second circuits include first and second supply rails. The apparatus includes a noise isolation circuit and a noise transference circuit. The noise isolation circuit is for coupling the first supply rails of the first and second circuits to prevent noise on the first supply rail of the first circuit from transferring to the first supply rail of the second circuit. The noise transference circuit is for coupling the second supply rails of the first and second circuits so that noise on the second supply rail of the first circuit is transferred to the second supply rail of the second circuit.

摘要翻译： 一种用于抑制来自第一电路的噪声对第二电路的性能的影响的装置，其中第一和第二电路在公共衬底上。 第一和第二电路中的每一个包括第一和第二电源轨。 该装置包括噪声隔离电路和噪声转移电路。 噪声隔离电路用于耦合第一和第二电路的第一电源轨，以防止第一电路的第一电源轨上的噪声转移到第二电路的第一电源轨。 噪声转移电路用于耦合第一和第二电路的第二电源轨，使得第一电路的第二电源轨上的噪声被传送到第二电路的第二电源轨。

公开(公告)号：US5982834A

公开(公告)日：1999-11-09

申请号：US854151

申请日：1997-05-09

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03L7/08 ,  H03L7/083 ,  H03L7/099 ,  H03L7/24 ,  H04L7/033 ,  H04L7/00

CPC分类号： H03L7/0995 ,  H03L7/24 ,  H04L7/033 ,  H03L7/083

摘要： A clock recovery system that allows recovery of a clock signal from a high speed, potentially small amplitude data stream. The invention uses a normally avoided property of a non-linear oscillator in the clock recovery system in order to lock the oscillator in phase to an incoming signal. This property relates a characteristic of an oscillator that an oscillator amplifies noise near its inherent frequency; and if the noise is large enough, the oscillator squelches the inherent oscillator frequency signal and outputs a signal locked in frequency and phase to the noise. The clock recovery system comprises a processing circuit, an oscillator, and a control circuit. The processing circuit processes an input data stream to generate a current signal as a first control signal based on data transitions in the input data stream. The first control signal is a "noise signal" to the oscillator. The control circuit outputs a voltage control signal as a second signal to the oscillator based on a difference between an output fed back from the oscillator and a reference frequency signal matching the frequency of the input data stream within a predetermined tolerance range. The second control signal controls the oscillator so that the frequency of the oscillator output is substantially equal to that of the input data stream. Therefore, according to the invention, the oscillator is controlled by the first control signal such that the oscillator output is phase-locked and thus also frequency-locked to the input data stream.

摘要翻译： 时钟恢复系统，允许从高速，潜在的小幅度数据流恢复时钟信号。 本发明在时钟恢复系统中使用非线性振荡器的正常避免的特性，以将振荡器锁相到输入信号。 该属性涉及振荡器的特征，振荡器放大其固有频率附近的噪声; 并且如果噪声足够大，则振荡器对固有的振荡器频率信号进行静噪，并输出锁定在频率和相位上的噪声信号。 时钟恢复系统包括处理电路，振荡器和控制电路。 处理电路基于输入数据流中的数据转换来处理输入数据流以产生作为第一控制信号的当前信号。 第一控制信号是振荡器的“噪声信号”。 控制电路基于从振荡器反馈的输出与在预定公差范围内与输入数据流的频率匹配的参考频率信号之间的差异，向振荡器输出电压控制信号作为第二信号。 第二控制信号控制振荡器，使得振荡器输出的频率基本上等于输入数据流的频率。 因此，根据本发明，振荡器由第一控制信号控制，使得振荡器输出被锁相，因此也被频率锁定到输入数据流。

公开(公告)号：US5068551A

公开(公告)日：1991-11-26

申请号：US586068

申请日：1990-09-21

申请人： Robert J. Bosnyak

发明人： Robert J. Bosnyak

IPC分类号： H03K19/0185 ,  H03K3/356

CPC分类号： H03K3/356113 ,  H03K3/356017

摘要： The present invention provides an ECL to CMOS level translation circuit which uses a dynamic, internally generated reference voltage to translate ECL level signals into CMOS level signals. The translator includes an input translation circuit which uses emitter-follower bipolar transistors for receiving and interpreting the ECL level signals and to generate the dynamic, internally generated reference potential, and an output circuit for outputting the CMOS signals.