公开(公告)号：US5132566A

公开(公告)日：1992-07-21

申请号：US557990

申请日：1990-07-25

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K19/003 ,  H03K17/081 ,  H03K19/088

CPC分类号： H03K17/08112

摘要： An output circuit capable of limiting an output current from a BiMOS semiconductor integrated circuit without adversely affecting an operational speed includes a plurality of bipolar transistors connected to form a Darlington circuit and at least one field effect transistor which can be either a P-channel or an N-channel transistor. The circuit is capable of removing rise current limitations of the bipolar transistors in the Darlington circuit during a normal operation by using a single MOS transistor to provide a branch circuit for the Darlington circuit, which limits the output current of the circuit under the specific condition that it provides a high level output and its output terminal is short-circuited to the ground.

摘要翻译： 能够限制来自BiMOS半导体集成电路的输出电流而不会不利地影响操作速度的输出电路包括连接形成达林顿电路的多个双极晶体管和至少一个场效应晶体管，其可以是P沟道或 N沟道晶体管。 该电路能够在正常操作期间消除达林顿电路中的双极晶体管的上升电流限制，通过使用单个MOS晶体管为达林顿电路提供分支电路，这限制了在特定条件下电路的输出电流， 它提供高电平输出，其输出端短路到地。

公开(公告)号：US4965465A

公开(公告)日：1990-10-23

申请号：US390998

申请日：1989-08-07

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K3/02 ,  H03K3/0232 ,  H03K3/033

CPC分类号： H03K3/0232

摘要： A monostable multivibrator comprising an input terminal receiving a trigger signal, a time constant circuit having at least a capacitor, a first pulse generator connected to the input terminal for generating a first pulse in synchronism with a leading edge of the trigger pulse, a first set-reset flipflop having a reset input connected to the first pulse generator and a Q output connected through a discharge circuit to one end of the capacitor, a first Schmitt circuit having an input connected to the one end of the capacitor and an output connected to a set input of the first flipflop, the first Schmitt circuit having a first threshold corresponding to a potential slightly higher than a potential of a logical low level so that the Schmitt circuit can detect a substantial discharge of the capacitor, a second Schmitt circuit having an input connected to the one end of the capacitor and having a second threshold corresponding to a potential slightly lower than a potential of a logical high level so that the Schmitt circuit can detect a substantial charge of the capacitor, a second pulse generator having an input connected to an output of the second Schmitt circuit for generating a second pulse in synchronism with a leading edge of the output of the second Schmitt, a second set-reset flipflop having a reset input connected to receive the second pulse from the second pulse generator and a Q output connected to an output terminal, and a logic gate having a first input connected to the output of the first pulse generator, a second input connected to the Q output of the second flipflop and an output connected to a set input of the second flipflop.

摘要翻译： 一种单稳态多谐振荡器，包括接收触发信号的输入端，具有至少电容器的时间常数电路，连接到输入端的第一脉冲发生器，用于产生与触发脉冲的前沿同步的第一脉冲;第一组 - 具有连接到第一脉冲发生器的复位输入的复位触发器和通过放电电路连接到电容器的一端的Q输出，具有连接到电容器的一端的输入的第一施密特电路和连接到电容器的一端的输出 设置第一触发器的输入，第一施密特电路具有对应于略高于逻辑低电平的电位的电位的第一阈值，使得施密特电路可以检测电容器的实质放电;第二施密特电路具有输入 连接到电容器的一端并且具有对应于稍低于逻辑高电位的电位的第二阈值 电平，使得施密特电路可以检测电容器的实质电荷，第二脉冲发生器具有连接到第二施密特电路的输出的输入，用于与第二施密特输出的前沿同步产生第二脉冲， 第二设定复位触发器，其具有连接用于接收来自第二脉冲发生器的第二脉冲的复位输入和连接到输出端子的＆amp; amp＆amp; Q输出;以及逻辑门，其具有连接到第一脉冲发生器的输出的第一输入， 连接到第二触发器的＆amp; Q＆amp; Q输出的第二输入端和连接到第二触发器的设定输入的输出。

公开(公告)号：US5006731A

公开(公告)日：1991-04-09

申请号：US416116

申请日：1989-10-02

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K19/0175 ,  H03K19/082 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/0826

摘要： A three state emitter coupled logic circuit has a logic circuit responsive to an input logic signal and a three state control signal, a difference circuit formed by two series combination of resistors and bipolar transistors coupled in parallel as well as a constant current source coupled between the difference circuit and a constant source, and an emitter follower circuit coupled to an intermediate node between one of the resistors and one of the bipolar transistors for producing an output signal, and a bypassing circuit is provided in parallel to the constant current source for increasing the amount of current passing through the difference circuit in the presence of the three state control signal of the active level, so that the voltage level at the intermediate node is varied out of the usual voltage range for the logic function mode, thereby the three state emitter coupled logic circuit being established in the high impedance state.

公开(公告)号：US4920284A

公开(公告)日：1990-04-24

申请号：US261634

申请日：1988-10-24

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K19/0185

CPC分类号： H03K3/356113 ,  H03K3/356017

摘要： In a semiconductor integrated circuit which contains, on the same chip, at least one logic circuit operating with a positive potential power and at least one logic circuit operating with a negative potential power, a level converter circuit is inserted between above logic circuits and is constituted of two series circuits each consisting of a P-channel MOSFET and an N-channel MOSFET connected in series between power lines supplied with the positive potential power and the negative potential power, and wirings to form a flip-flop circuit with each one MOSFET in respective series circuits.

摘要翻译： 在一个半导体集成电路中，在相同的芯片上包含至少一个以正电位工作的逻辑电路和至少一个以负电位工作的逻辑电路，电平转换器电路被插在上述逻辑电路之间，并被构成 两个串联电路由P沟道MOSFET和N沟道MOSFET组成，串联连接在提供正电位和负电位的电源线之间，以及布线以形成每个MOSFET的触发电路 各自的串联电路。

公开(公告)号：US5278463A

公开(公告)日：1994-01-11

申请号：US1552

申请日：1993-01-06

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K19/08 ,  H03K19/013 ,  H03K19/088 ,  H03K19/0944 ,  H03K19/02

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： It is purposed to ensure both high speed operation and low power consumption in an output section of a Bi-CMOS type TTL logic circuit. For this purpose, impedances of a base driving part (a series circuit of a MOS transistor 9 and a resistor 11) and a collector driving part A (a resistor 12) of a bipolar transistor 1 are brought into low impedances only when the bipolar transistor 1 is changed from an off-to on-state thereof. To achieve the just-mentioned operation, potential on an output 30 is detected by an inverter 16 and on the basis of an output from the inverter 16 both MOS transistors 17, 19 are on-controlled to substantially short-circuit the resistors 11, 12. When the transistor 1 stays at its on-state, both transistors 17, 19 have been switched off, so that base and collector currents of the transistor 1 have been conducted through the resistors 11, 12 to permit the resistors 11, 12 to be greater. Thus, low power consumption is attained.

摘要翻译： 旨在确保Bi-CMOS型TTL逻辑电路的输出部分的高速运行和低功耗。 为此，双极晶体管1的基极驱动部分（MOS晶体管9和电阻器11的串联电路）和集电极驱动部分A（电阻器12）的阻抗仅在双极晶体管 1从断开状态改变为开状态。 为了实现刚刚提及的操作，反相器16检测输出端30的电位，并且基于反相器16的输出，两个MOS晶体管17,19都受控制，使得电阻器11,12基本上短路 当晶体管1保持在其导通状态时，两个晶体管17,19都被切断，使得晶体管1的基极和集电极电流已经被传导通过电阻器11,12，以允许电阻器11,12为 更大 因此，实现了低功耗。

公开(公告)号：US4977339A

公开(公告)日：1990-12-11

申请号：US303845

申请日：1989-01-30

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K19/0185

CPC分类号： H03K19/018507

摘要： A semiconductor integrated circuit comprises a positive voltage line, a negative voltage line, a ground line, a first circuit connected between the ground line and one of the positive voltage line and the negative voltage line so as to be driven by a voltage difference between the ground line and the one of the positive voltage line and the negative voltage line, and a second circuit connected between the ground line and the other of the positive voltage line and the negative voltage line so as to be driven by a voltage difference between the ground line and the other of the positive voltage line and the negative voltage line. A signal level conversion circuit includes a MOS transistor having a gate connected to an output of the first circuit and a drain connected through a resistor to the ground line. A source of the transistor is connected to the other of the positive voltage line and the negative voltage line, and the drain of the transistor is connected to an input of the second circuit. This transistor has its threshold voltage whose absolute value is larger than an absolute value of a voltage difference between the ground line and the other of the positive voltage line and the negative voltage line.

公开(公告)号：US4719367A

公开(公告)日：1988-01-12

申请号：US5989

申请日：1987-01-21

申请人： Akira Denda

发明人： Akira Denda

IPC分类号： H03K3/027 ,  H03K3/037 ,  H03K3/29 ,  H03K5/153 ,  H03K17/60 ,  H03K19/092

CPC分类号： H03K3/0377

摘要： For improvement in switching speed, there is provided a Schmit trigger circuit comprising a high-voltage supply line, a low-voltage supply line, a series combination of a bipolar transistor and a resistor provided between the high-voltage supply line and the low-voltage supply line, the bipolar transistor having a base node connected to an input terminal, an intermediate node provided between the bipolar transistor and the resistor, a logic gate having an output node and two input nodes connected to the input terminal and the intermediate node, respectively, and a field effect transistor operative to establish or block a current path between the intermediate node and one of the high-voltage supply line and the low-voltage supply line, the field effect transistor having a gate node connected to the output node of the logic gate.

摘要翻译： 为了提高开关速度，提供了一种施密特触发电路，其包括高压电源线，低压电源线，双极晶体管和设置在高压电源线和低压电源线之间的电阻器的串联组合， 所述双极晶体管具有连接到输入端子的基极节点，设置在所述双极晶体管和所述电阻器之间的中间节点，具有输出节点的逻辑门和连接到所述输入端子和所述中间节点的两个输入节点， 以及场效应晶体管，其操作用于建立或阻断中间节点与高压电源线和低电压电源线中的一个之间的电流路径，场效应晶体管具有连接到输出节点的输出节点的栅极节点 逻辑门。