发明授权
US4920284A CMOS level converter circuit with reduced power consumption 失效
CMOS电平转换器电路,功耗降低

  • 专利标题: CMOS level converter circuit with reduced power consumption
  • 专利标题(中): CMOS电平转换器电路,功耗降低
  • 申请号: US261634
    申请日: 1988-10-24
  • 公开(公告)号: US4920284A
    公开(公告)日: 1990-04-24
  • 发明人: Akira Denda
  • 申请人: Akira Denda
  • 申请人地址: JPX Tokyo
  • 专利权人: NEC Corporation
  • 当前专利权人: NEC Corporation
  • 当前专利权人地址: JPX Tokyo
  • 优先权: JPX62-267794 19871022
  • 主分类号: H03K5/02
  • IPC分类号: H03K5/02 H03K3/356 H03K19/0185
CMOS level converter circuit with reduced power consumption
摘要:
In a semiconductor integrated circuit which contains, on the same chip, at least one logic circuit operating with a positive potential power and at least one logic circuit operating with a negative potential power, a level converter circuit is inserted between above logic circuits and is constituted of two series circuits each consisting of a P-channel MOSFET and an N-channel MOSFET connected in series between power lines supplied with the positive potential power and the negative potential power, and wirings to form a flip-flop circuit with each one MOSFET in respective series circuits.
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