公开(公告)号：US06891708B2

公开(公告)日：2005-05-10

申请号：US09944118

申请日：2001-09-04

申请人： Takaharu Hutamura ,  Shoichi Okuda

发明人： Takaharu Hutamura ,  Shoichi Okuda

IPC分类号： H02M1/00 ,  H02M1/08 ,  H03K17/00 ,  H03K17/04 ,  H03K17/66 ,  H03K17/687 ,  H03K19/0175 ,  H02H3/20

CPC分类号： H02M1/08 ,  H03K17/666 ,  H03K17/6877 ,  H03K2217/0036 ,  Y10T307/858

摘要： A drive circuit for driving a switching element is provided which includes a high-side switching circuit connected between power supply lines, a low-side switching circuit connected in series with the high-side switching circuit through an output terminal leading to the switching element, and a voltage detector detecting a voltage appearing at the output terminal. When the voltage detected by the voltage detector is lower than a given off-decision voltage, that is, when the switching element is placed in the off-state, the low-side switching circuit is brought into the off-state, thereby reducing the current consumption thereof.

摘要翻译： 提供一种用于驱动开关元件的驱动电路，其包括连接在电源线之间的高侧开关电路，通过通向开关元件的输出端与高侧开关电路串联连接的低侧开关电路， 以及电压检测器，检测出现在输出端的电压。 当由电压检测器检测到的电压低于给定的断开电压时，即当开关元件处于截止状态时，低侧开关电路进入截止状态，从而减少 电流消耗。

公开(公告)号：US5118973A

公开(公告)日：1992-06-02

申请号：US570857

申请日：1990-08-22

申请人： Toshiaki Sakai ,  Taichi Saitoh

发明人： Toshiaki Sakai ,  Taichi Saitoh

IPC分类号： H01L27/082 ,  H01L21/8222 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K19/086

摘要： An improved emitter coupled logic circuit suitable for high speed logic operation independent of capacitive load. With previous circuits as the load to be driven become heavier, the capacitive load required a longer time for discharge and the output signal was dulled, resulting in adverse effect on the logic operation when the output changed to a low level from a high level. A pulse has also been previously applied to a pull-down transistor connected between the output and a power source through a capacitor from an inverted phase output to actively discharge the capacitive load. However, when the capacitor is connected to the output it hinders the switching speed of a current switch. In the present invention, a transistor is provided an input circuit and a pulse is applied to a pull-down transistor from the transistor. As a result, an extra capacitive element is not connected to the output end, but a pulse is applied to the pull-down transistor. Accordingly, even if the capacitive load becomes heavier, the speed of the circuit is not harmed.

摘要翻译： 一种改进的发射极耦合逻辑电路，适用于独立于电容负载的高速逻辑运算。 随着驱动负载变得越来越重，电容负载需要较长的放电时间，输出信号变钝，当输出从高电平变为低电平时，对逻辑运算产生不利影响。 先前已经将脉冲施加到通过来自反相输出的电容器连接在输出和电源之间的下拉晶体管，以主动放电容性负载。 然而，当电容器连接到输出时，它阻碍了电流开关的开关速度。 在本发明中，晶体管被提供有输入电路，并且脉冲从晶体管施加到下拉晶体管。 结果，额外的电容元件不连接到输出端，但是脉冲被施加到下拉晶体管。 因此，即使容性负载变重，电路的速度也不会受到损害。

公开(公告)号：US4999520A

公开(公告)日：1991-03-12

申请号：US330461

申请日：1989-03-30

申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K3/2885 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K19/086

摘要： A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

摘要翻译： 一种半导体集成电路，其中输入电路由相位分离电路形成，该相位分离电路由输出来自集电极的反相输出和从发射极输出的非反相输出的双极晶体管构成，射极跟随器输出电路由反相输出驱动 同相分流电路，射极跟随器输出电路的发射极负载由晶体管形成，发射极负载晶体管通过非反相输出的上升沿的待充电电容的充电电流暂时驱动导通 的相分离电路。

公开(公告)号：US4910416A

公开(公告)日：1990-03-20

申请号：US164209

申请日：1988-03-04

申请人： Michael D. Salcone

发明人： Michael D. Salcone

IPC分类号： H03K17/042 ,  H03K17/66

CPC分类号： H03K17/04213 ,  H03K17/666

摘要： The present invention provides an improved device for minimizing the time delays associated with turning on and off the power switches or power transistors in a standard totem pole configuration. An improved saturation detector monitors each transistor to determine when it is in saturation and generates a feedback signal which is combined with the input signal to generate the appropriate time delay needed to improve the switching time of the transistor.

摘要翻译： 本发明提供了一种改进的装置，用于最小化在标准图腾柱结构中打开和关闭电源开关或功率晶体管相关的时间延迟。 改进的饱和检测器监视每个晶体管以确定其何时处于饱和状态，并产生与输入信号组合的反馈信号，以产生改善晶体管开关时间所需的适当时间延迟。

公开(公告)号：US4904904A

公开(公告)日：1990-02-27

申请号：US199313

申请日：1988-05-26

申请人： Humberto T. Zarate

发明人： Humberto T. Zarate

IPC分类号： H02M7/5383 ,  H02M7/53846 ,  H02M7/53862 ,  H03K17/60 ,  H03K17/66 ,  H05B41/282

CPC分类号： H02M7/53862 ,  H02M7/53846 ,  H03K17/601 ,  H03K17/666 ,  H05B41/2825 ,  Y10S315/05 ,  Y10S315/07

摘要： An electronic transformer system for powering gaseous discharge lamps includes an output transformer having a load connected to a secondary winding and having a power storage capacitor connected in series with a primary winding, a charging transistor connecting one end of the series combination to one polarity terminal of a voltage doubler DC power source, the other end of the series combination connected to the other polarity terminal of the power source, a discharging transistor connected across the series connected primary and capacitor, and an oscillator connected through a coupling transformer to the bases of the transistors. The oscillators alternately causes the transistors to switch into conduction to thereby alternately cause the charging and discharging of the capacitor through the output transformer. The charging and discharging characteristics of the capacitor result in the turn off of the transistors occurring at low current levels whereby turn off of the transistors is accelerated.

摘要翻译： 一种用于为气体放电灯供电的电子变压器系统包括一个输出变压器，其具有与次级绕组连接的负载，并具有与初级绕组串联连接的功率存储电容器，将串联组合的一端连接到一个极性端子的充电晶体管 电压倍增器直流电源，串联组合的另一端连接到电源的另一极性端子，连接在串联连接的初级和电容器上的放电晶体管，以及通过耦合变压器连接到基极的振荡器 晶体管。 振荡器交替地使晶体管切换到导通，从而交替地使电容器通过输出变压器进行充电和放电。 电容器的充电和放电特性导致在低电流水平下发生晶体管的关断，从而加速了晶体管的关断。

公开(公告)号：US4638189A

公开(公告)日：1987-01-20

申请号：US626377

申请日：1984-06-29

申请人： George Geannopoulos ,  Cyrus Tsui ,  Mark Fitzpatrick ,  Andy Chan

发明人： George Geannopoulos ,  Cyrus Tsui ,  Mark Fitzpatrick ,  Andy Chan

IPC分类号： H03K19/177 ,  H03K17/66 ,  H03K19/173 ,  H03K19/20 ,  G06F11/28 ,  H03K19/003 ,  H03K19/082

CPC分类号： H03K19/1736 ,  H03K17/666

摘要： The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.

摘要翻译： 本发明以N逻辑输入信号的逻辑和功能组合，其中N是大于或等于1的选择的正整数，并且可编程地提供直接AND输出信号或NAND输出信号。 本发明使用数据路径中的最小数量的组件，逻辑输入引线和逻辑输出引线之间来实现。 数据路径中的最小组件减少了由电路引入的传播延迟。 本发明通过提供连接到同一组N个逻辑输入信号的两个与门来实现这一点。 一个与门的输出信号由具有使能/禁止输入引线的反相器反相。 另一个与门的输出信号由两个反相器反相两次。 第二个反相器具有使能/禁止输入引线。 提供了用于通过使能/禁止输入引线独占地使能两个逆变器中的一个或另一个的装置。 因此，将一次反相信号提供给输出引线，或将两次反相信号提供给输出引线。

公开(公告)号：US4251742A

公开(公告)日：1981-02-17

申请号：US28367

申请日：1979-04-09

申请人： Howard R. Beelitz

发明人： Howard R. Beelitz

IPC分类号： H03K17/00 ,  H03K17/66 ,  H03K3/26 ,  H03K23/14

CPC分类号： H03K17/666 ,  H03K2217/0036

摘要： A current driver circuit using a two-level current source for switching PIN diodes. The driver is responsive to a binary signal control voltage for providing a respective forward-bias current or reverse-bias voltage. The two-level current source, responsive to output voltage, is included in the driver circuit to supply one of two current levels when the driver is conditioned to forward-bias the diode. When the output voltage is below a predetermined threshold value, a first level of current is supplied; when the output voltage is above the predetermined value, a second level of current, generally larger than the first current, is provided. The disclosed technique reduces peak instantaneous power dissipation in the driver by avoiding the simultaneous condition of high voltage and high current.

摘要翻译： 一个使用二电平电流源切换PIN二极管的电流驱动电路。 驱动器响应二进制信号控制电压以提供相应的正向偏置电流或反向偏置电压。 当驱动器被调节以对二极管进行正向偏置时，响应于输出电压的两电平电流源被包括在驱动器电路中以提供两个电流电平之一。 当输出电压低于预定阈值时，提供第一电平电平; 当输出电压高于预定值时，提供通常大于第一电流的第二电平电平。 所公开的技术通过避免高电压和高电流的同时条件来降低驱动器中的峰值瞬时功率消耗。

公开(公告)号：US3710147A

公开(公告)日：1973-01-09

申请号：US3710147D

申请日：1971-06-29

申请人： PLESSEY HANDEL INVESTMENT AG

发明人： LEE M

IPC分类号： H03K17/10 ,  H03K17/66 ,  H03K17/56

CPC分类号： H03K17/662 ,  H03K17/10 ,  H03K17/666

摘要： A high voltage switch arrangement comprising switches each defined by cascaded transistors connected effectively in the arms of a bridge for switching a high voltage across a capacitive load so that an a.c. voltage is supplied through the load when the bridge is fed from a d.c. source and the switches operated sequentially.

摘要翻译： 一种高电压开关装置，包括开关，每个开关由层叠的晶体管限定，该晶体管有效连接在桥臂中，用于在电容性负载上切换高电压， 当电桥从直流电源供电时，通过负载提供电压。 源和开关顺序操作。

公开(公告)号：US3488524A

公开(公告)日：1970-01-06

申请号：US3488524D

申请日：1966-10-18

申请人： FABRI TEK INC

发明人： PARROTT EUGENE F W JR

IPC分类号： G11C11/06 ,  H03K17/66 ,  H03K17/56

CPC分类号： G11C11/06007 ,  H03K17/666

公开(公告)号：US07701278B2

公开(公告)日：2010-04-20

申请号：US12069281

申请日：2008-02-08

申请人： Reinhard Herzer ,  Matthias Rossberg ,  Bastian Vogler

发明人： Reinhard Herzer ,  Matthias Rossberg ,  Bastian Vogler

IPC分类号： H03L5/00

CPC分类号： H03K17/08122 ,  H03K17/666 ,  H03K19/018521

摘要： A TOP level switch for use in a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The TOP level shifter transmits an input signal from drive logic to a TOP driver. In this case, the TOP level shifter is designed as an arrangement of an UP and a DOWN level shifter path, as well as a downstream signal evaluation circuit. In the associated method for transmission of this input signal, the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN, or both, level shifter paths emit a signal to the respectively associated input of the signal evaluation circuit.

摘要翻译： 一种用于具有由两个电源开关形成的半桥电路的功率电子系统的驱动电路中的TOP电平开关，第一所谓的TOP开关和第二所谓的BOT开关，它们串联连接。 TOP电平移位器将驱动逻辑的输入信号传输到TOP驱动器。 在这种情况下，TOP电平移位器被设计为UP和DOWN电平移位器路径以及下行信号评估电路的布置。 在用于传输该输入信号的相关方法中，当UP或DOWN或两个电平移位器路径向信号评估电路的相应输入端发射信号时，信号评估电路将输出信号传递给TOP驱动器 。