公开(公告)号：US20250046746A1

公开(公告)日：2025-02-06

申请号：US18718192

申请日：2022-04-11

Applicant: Mitsubishi Electric Corporation

Inventor： Koji MISAKI

IPC: H01L23/00 ,  H01L23/12

Abstract: A hollow package includes a device substrate; a lid substrate provided above the device substrate; a first sealing ring provided on an upper surface of the device substrate; a second sealing ring provided on a lower surface of the lid substrate so as to face the first sealing ring; a seal layer that bonds the first sealing ring and the second sealing ring; and a functional element provided in a hollow portion surrounded by the device substrate, the lid substrate, the first sealing ring, the second sealing ring, and the seal layer, wherein the first sealing ring or the second sealing ring has a corner portion in a planar view, and the first sealing ring or the second sealing ring has a recess, which is recessed in a direction perpendicular to the upper surface of the device substrate, locally formed in a portion including the corner portion.

公开(公告)号：US20240417244A1

公开(公告)日：2024-12-19

申请号：US18701399

申请日：2022-09-20

Applicant: Schott AG

Inventor： Jens Ulrich Thomas ,  Antti Määttänen ,  Petri Rokka

IPC: B81C1/00 ,  B23K26/21 ,  B23K101/40 ,  H01L21/54 ,  H01L21/78 ,  H01L23/06 ,  H01L23/12

Abstract: An enclosure is shown, comprising at least a first substrate having an outer surface and a second substrate having an outer surface, wherein the first substrate and the second substrate are arranged next to each other in such a way, that an inner surface of the first substrate is adjacent to an inner surface of the second substrate, wherein the second substrate is transparent at least in part and/or at least for a bandwidth of wavelengths, at least one laser weld zone containing an information pattern in the enclosure, wherein the at least one laser weld zone extends from within the first substrate to within the second substrate and permanently joins the first substrate to the second substrate.

公开(公告)号：US20240395792A1

公开(公告)日：2024-11-28

申请号：US18790195

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/10

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US20240379610A1

公开(公告)日：2024-11-14

申请号：US18781200

申请日：2024-07-23

Applicant: ROHM CO., LTD.

Inventor： Kazunori FUJI

IPC: H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495

Abstract: Semiconductor device A1 of the disclosure includes: semiconductor element 11 having element obverse surface 11a and element reverse surface 11b spaced apart from each other in z direction (first direction) with first region 111 formed on the element obverse surface 11a; metal plate 31 (electrode member) disposed on the element obverse surface 11a and electrically connected to the first region 111; electrically conductive substrate 22A (first conductive member) disposed to face the element reverse surface 11b and bonded to the semiconductor element 11; electrically conductive substrate 22B (second conductive member) spaced apart from the conductive substrate 22A (first conductive member); and lead member 5 (connecting member) electrically connecting the metal plate 31 (electrode member) and the conductive substrate 22B (second conductive member). The lead member 5 (connecting member) is bonded to the metal plate 31 (electrode member) by laser welding. The semiconductor device of this configuration provides improved reliability.

公开(公告)号：US20240355900A1

公开(公告)日：2024-10-24

申请号：US18302010

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Man-Nung Su

IPC: H01L29/66 ,  H01L23/00 ,  H01L23/12 ,  H01L29/775

CPC classification number: H01L29/66439 ,  H01L23/12 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/66742 ,  H01L29/775 ,  H01L24/94 ,  H01L29/0673 ,  H01L29/42392 ,  H01L2224/29138 ,  H01L2224/29186 ,  H01L2224/8301 ,  H01L2224/83193 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a device layer including a front side and a back side opposite to each other, a bonding layer disposed on the back side of the device layer, and a carrier substrate underlying the bonding layer. The device layer includes source/drain (S/D) structures, semiconductor channel layers connecting the S/D structures, and a gate structure disposed between the S/D structures and around each of the semiconductor channel layers, where the back side is planar and includes the S/D structures and the gate structure.

公开(公告)号：US12119338B2

公开(公告)日：2024-10-15

申请号：US18447655

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/44 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US12080675B2

公开(公告)日：2024-09-03

申请号：US17430691

申请日：2020-02-10

Applicant: ROHM CO., LTD.

Inventor： Kazunori Fuji

IPC: H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/40 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/37 ,  H01L24/84 ,  H01L2224/32225 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/84893

Abstract: Semiconductor device A1 of the disclosure includes: semiconductor element 11 having element obverse surface 11a and element reverse surface 11b spaced apart from each other in z direction (first direction) with first region 111 formed on the element obverse surface 11a; metal plate 31 (electrode member) disposed on the element obverse surface 11a and electrically connected to the first region 111; electrically conductive substrate 22A (first conductive member) disposed to face the element reverse surface 11b and bonded to the semiconductor element 11; electrically conductive substrate 22B (second conductive member) spaced apart from the conductive substrate 22A (first conductive member); and lead member 5 (connecting member) electrically connecting the metal plate 31 (electrode member) and the conductive substrate 22B (second conductive member). The lead member 5 (connecting member) is bonded to the metal plate 31 (electrode member) by laser welding. The semiconductor device of this configuration provides improved reliability.

公开(公告)号：US12062635B2

公开(公告)日：2024-08-13

申请号：US17451693

申请日：2021-10-21

Applicant: Micron Technology, Inc.

Inventor： Po Chih Yang ,  Yu Jen Chen ,  Po Chen Kuo ,  Shih Wei Liang

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/41 ,  H01L21/563 ,  H01L21/76871 ,  H01L23/3157 ,  H01L24/09 ,  H01L24/35 ,  H01L25/0657

Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

公开(公告)号：US11984373B2

公开(公告)日：2024-05-14

申请号：US17522327

申请日：2021-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Lopez

IPC: H01L23/31 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52 ,  H01S5/02218 ,  H01S5/068

CPC classification number: H01L23/3114 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

公开(公告)号：US11955409B2

公开(公告)日：2024-04-09

申请号：US17148257

申请日：2021-01-13

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/12 ,  H01L23/66

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/12 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6638

Abstract: A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.