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公开(公告)号：US20240192745A1
公开(公告)日：2024-06-13
申请号：US18315678
申请日：2023-05-11
申请人： NXP USA, Inc.
发明人： Kumar Abhishek , Neha Srivastava , Yi Zheng , Nishant Kumar
IPC分类号： G06F1/24
CPC分类号： G06F1/24
摘要： Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.
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公开(公告)号：US12008384B2
公开(公告)日：2024-06-11
申请号：US17220765
申请日：2021-04-01
申请人： SAP SE
发明人： Markus Boehm , Jan Aalmink
CPC分类号： G06F9/44505 , G06F16/2282 , G06F16/284 , G06F16/9024
摘要： Systems, methods, and computer media are described for process-oriented application configuring using semantic mapping. Desired application processes can be identified by a user, and a semantic map can be generated linking the application processes, and components of processes, to corresponding configuration objects that are used to implement the processes in the application. Configuration objects can be settings, objects, functions, user interface features, executables, etc. The semantic map thus bridges between the process-oriented view of an application and the functional, implementation-oriented view of the application. The applications can then be configured using the configuration objects identified and linked by the semantic map.
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公开(公告)号：US11983073B2
公开(公告)日：2024-05-14
申请号：US17874952
申请日：2022-07-27
IPC分类号： G06F15/177 , G06F1/24 , G06F9/00 , G06F9/4401 , G06F11/14
CPC分类号： G06F11/1417 , G06F1/24 , G06F9/4405
摘要： Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
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公开(公告)号：US20240111650A1
公开(公告)日：2024-04-04
申请号：US18476706
申请日：2023-09-28
发明人： Xing Peng , Cui Zhineng , Jilu Sun , YuJie Zhou , Wenjun Ji , Tyan-Shu Jou
CPC分类号： G06F11/3072 , G06F1/24
摘要： During operation, an electronic device may receive, associated with a computer, a packet or a frame that includes a dynamic power reset pattern, where the dynamic power reset pattern specifies temporal pattern of power resets. Then, the electronic device may detect multiple power resets, where a given detected power reset in the detected power resets involves activation of a power reset button in the electronic device. Moreover, the electronic device may compute a detected power reset pattern, where the detected power reset pattern includes a detected temporal pattern of detected power resets. Next, the electronic device may compare the dynamic power reset pattern and the detected power reset pattern. Furthermore, based at least in part on a result of the comparison, the electronic device may at least selectively provide, to the computer, the result of the comparison.
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公开(公告)号：US11923840B1
公开(公告)日：2024-03-05
申请号：US18180167
申请日：2023-03-08
申请人： NXP B.V.
IPC分类号： G06F1/24 , G06F1/28 , H03K17/687 , H03K19/0185
CPC分类号： H03K17/6872 , G06F1/28 , H03K19/018571
摘要： A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.
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公开(公告)号：US11921530B2
公开(公告)日：2024-03-05
申请号：US17383391
申请日：2021-07-22
发明人： Shih-Chung Wang , Cheng-Yu Shu , Wei-Chieh Lin
摘要： A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.
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7.发明公开公开(公告)号：US20240053808A1
公开(公告)日：2024-02-15
申请号：US18356055
申请日：2023-07-20
申请人： NXP USA, Inc.
发明人： Alaa Eldin Y. El Sherif , Jean-Philippe Meunier , Loic Hureau , Thomas Henry Luedeke , Maxime Clairet
摘要： A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.
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公开(公告)号：US11853773B2
公开(公告)日：2023-12-26
申请号：US16405395
申请日：2019-05-07
IPC分类号： G06F1/24 , G06F9/00 , G06F9/445 , G06N3/08 , G06F9/4401
CPC分类号： G06F9/4451 , G06F9/4415 , G06N3/08
摘要： Aspects of the disclosure relate to computer hardware and software for managing a field device (e.g., a transmitter, an actuator, a valve, a switch, a sensor, a power supply, a meter, or the like, used in one or more pieces of equipment that process one or more input chemicals to create one or more products in a chemical plant, a petrochemical plant, a refinery, or the like) by using an interactive automation/self-learning program module installed in a computing device (e.g., a mobile device). Some aspects of the disclosure provide techniques that may enable a computing device to connect to a field device; automatically identify the field device; provide guidance to manage the connected field device; receive input corresponding to the guidance; and/or manage the field device based on the input.
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公开(公告)号：US11809258B2
公开(公告)日：2023-11-07
申请号：US16820307
申请日：2020-03-16
申请人： Apple Inc.
发明人： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Richard Solotke
IPC分类号： G06F1/26 , G06F1/32 , G06F1/3234 , G06F13/40 , G06F13/42 , G06F1/3203 , G06F1/3287 , G06F9/30 , G06F9/4401 , G06F1/24
CPC分类号： G06F1/325 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F9/3004 , G06F9/4411 , G06F9/4418 , G06F13/404 , G06F13/4221 , G06F13/4273 , G06F13/4278 , G06F1/24 , Y02D10/00
摘要： Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
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公开(公告)号：US11797679B2
公开(公告)日：2023-10-24
申请号：US17386779
申请日：2021-07-28
申请人： Dell Products, L.P.
发明人： Eugene David Cho , Mario Alberto Sanchez , Akkiah Choudary Maddukuri , Marshal F. Savage , Paul W. Vancil
CPC分类号： G06F21/572 , G06F11/0772 , G06F21/53 , G06F21/575 , G06F21/602 , G06F21/64 , G06F9/4401 , G06F2221/2149
摘要： An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes instructions for executing a bootloader to verify an integrity of a first firmware stack, and boot the first firmware stack on a first processor. Once booted, the first firmware stack verifies the integrity of a first code segment on a second processor that is also used to execute a custom BMC firmware stack. The first code segment is executed to verify the integrity of one or more vendor supplied code segments executed on the second processor.
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