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    SYSTEM AND METHOD TO DESIGN PHOTONIC CIRCUITS FOR PREPARING GAUSSIAN AND NON-GAUSSIAN STATES
    3.
    发明申请
    SYSTEM AND METHOD TO DESIGN PHOTONIC CIRCUITS FOR PREPARING GAUSSIAN AND NON-GAUSSIAN STATES 有权

    公开(公告)号：US20230130156A1

    公开(公告)日：2023-04-27

    申请号：US17512530

    申请日：2021-10-27

    申请人： XANADU QUANTUM TECHNOLOGIES INC.

    发明人： Filippo M. MIATTO ,  Nicolas QUESADA

    IPC分类号： G06F30/32 ,  G06N10/00

    摘要： Embodiments described herein provide systems and methods for optimizing a Gaussian representation to design photonic circuits for preparing a given target quantum state. The systems and methods internally consider and optimize quantum representations (e.g., Gaussian transformations, Gaussian and non-Gaussian states). In some embodiments, the systems and methods may produce optimal Gaussian transformations or states. In some embodiments, the systems and methods extract circuit parameters from an optimal Gaussian transformation to produce quantum circuits or designs for generating the optimal states. Embodiments described herein relate to systems and methods for optimizing a Gaussian transformation for state generation.

    SYSTEM AND METHOD FOR DIGITAL CIRCUIT EMULATION WITH HOMOMORPHIC ENCRYPTION
    4.
    发明申请
    SYSTEM AND METHOD FOR DIGITAL CIRCUIT EMULATION WITH HOMOMORPHIC ENCRYPTION 有权

    公开(公告)号：US20220360427A1

    公开(公告)日：2022-11-10

    申请号：US17737480

    申请日：2022-05-05

    申请人： Duality Technologies, Inc.

    发明人： David Bruce COUSINS

    IPC分类号： H04L9/00 ,  G06F30/32

    摘要： Systems and methods for digital circuit emulation with homomorphic encryption include: receiving, by a hardware design tool chain, a customization file containing a predetermined set of one or more cells; converting, by the hardware design tool chain, a first digital circuit representation in a set of hardware design language (HDL) files into a second digital circuit representation based on the predetermined set of cells in the customization file; receiving, by an encrypted circuit emulator, a set of encrypted inputs; and executing, by the encrypted circuit emulator, the second digital circuit representation using the set of encrypted inputs to generate a set of encrypted outputs.

    SYSTEMS AND METHODS FOR INCORPORATING MANUFACTURING, TESTING AND AFTER SALE DATA IN A PRINTED CIRCUIT BOARD USING BLOCKCHAIN
    5.
    发明申请
    SYSTEMS AND METHODS FOR INCORPORATING MANUFACTURING, TESTING AND AFTER SALE DATA IN A PRINTED CIRCUIT BOARD USING BLOCKCHAIN 有权

    公开(公告)号：US20220284160A1

    公开(公告)日：2022-09-08

    申请号：US17574876

    申请日：2022-01-13

    申请人： GOODRICH CORPORATION

    发明人： Elangovan Palaniappan

    IPC分类号： G06F30/32

    摘要： A method for controlling a PCBA data distributed ledger located on blockchain network and a system for implementing the method are disclosed. The method may comprise scanning, by an optical label reader, an optical label located on a PCB and decoding, by an entity device, the optical label. The method may further include receiving, by a ledger controller, a request to access a distributed ledger from the entity device; verifying, by the blockchain nodes, a public key received from the entity device; determining, by the ledger controller, whether a private key received from the entity device matches a stored login credential; and determining whether to allow the entity device to access at least a first block on the distributed ledger.

    Systems and methods for optimizing scan pipelining in hierarchical test design
    6.
    发明授权
    Systems and methods for optimizing scan pipelining in hierarchical test design 有权

    公开(公告)号：US11409931B1

    公开(公告)日：2022-08-09

    申请号：US17203497

    申请日：2021-03-16

    申请人： CADENCE DESIGN SYSTEMS, INC.

    发明人： Jagjot Kaur ,  William Scott Gaskins

    IPC分类号： G06F30/333 ,  G06F30/30 ,  G06F30/32 ,  G06F30/396 ,  G06F119/12 ,  G01R31/3185 ,  G01R31/317

    摘要： A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.