- 专利标题： CFET architecture for balancing logic library and SRAM bitcell
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申请号： US16995556申请日： 2020-08-17
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公开(公告)号： US11837280B1公开(公告)日： 2023-12-05
- 发明人: Victor Moroz , Deepak Sherlekar , Jamil Kawa
- 申请人： Synopsys, Inc.
- 申请人地址： US CA Mountain View
- 专利权人： Synopsys, Inc.
- 当前专利权人： Synopsys, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Lowenstein Sandler LLP
- 主分类号： G11C11/412
- IPC分类号： G11C11/412 ; G06F30/32 ; H10B10/00
摘要：
The independent claims of the present disclosure signify a concise description of embodiments. An electronic structure based on complementary-field effect transistor (CFET) architecture is disclosed. The electronic structure comprises an n-channel metal-oxide-semiconductior (NMOS) gate-all-around (GAA) channel in a first layer, and p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer. The PMOS GAA channel is wider compared to the NMOS GAA channel. The first layer is above the second layer and separated by a dielectric layer.
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