公开(公告)号：US20190103839A1

公开(公告)日：2019-04-04

申请号：US15719961

申请日：2017-09-29

申请人： NXP USA, INC.

发明人： JAEYOUNG LEE ,  NADER ROHANI

IPC分类号： H03F1/02 ,  H03F3/193 ,  H03F3/45

CPC分类号： H03F1/0205 ,  H03F1/26 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45179 ,  H03F2200/294 ,  H03F2200/333 ,  H03F2200/75 ,  H03F2203/45101 ,  H03F2203/45296 ,  H03F2203/45306 ,  H03F2203/45316 ,  H03F2203/45394 ,  H03F2203/45638 ,  H03F2203/45686

摘要： An integrated circuit includes a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of a first differential pair of transistors. A second high-pass filter includes an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors. The second signal may be a complementary signal of the first signal. A second differential pair of transistors includes control electrodes coupled to a first voltage supply terminal. A boost circuit is coupled between the second differential pair of transistors and the first voltage supply terminal. A low-pass filter is coupled between the first differential pair of transistors and the second differential pair of transistors.

公开(公告)号：US09979188B2

公开(公告)日：2018-05-22

申请号：US15027448

申请日：2016-03-22

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Fenghao Mu

IPC分类号： H02H9/04 ,  H03H11/28 ,  H04B5/00 ,  H04L25/00 ,  H04L25/02 ,  H04B7/0413 ,  H01L25/065 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L25/0655 ,  H01L27/0292 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/91 ,  H03F2203/45228 ,  H03F2203/45268 ,  H03F2203/45306 ,  H03F2203/45506 ,  H03F2203/45638 ,  H03F2203/45686 ,  H03F2203/45731 ,  H03H11/28 ,  H04B5/0075 ,  H04B7/0413 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0292

摘要： An interface for inter-chip communication, comprises a transmitter part (TX) for transmitting a differential signal and a receiver part (RX) for receiving the differential signal, the transmitter part (TX) being provided in a first integrated circuit chip (CHIP A) and the receiver part (RX) being provided in a second integrated circuit chip (CHIP B). The transmitter part (TX) comprises a first transistor (Tx1) and a second transistor (Tx2) arranged in a common source configuration, and the receiver part (RX) comprises a third transistor (TR1) and a fourth transistor (TR2) arranged in a common gate configuration. Current flowing in the receiver part (RX) also flows through the transmitter part (TX).

公开(公告)号：US20180109257A1

公开(公告)日：2018-04-19

申请号：US15790196

申请日：2017-10-23

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Richard Scott BURTON ,  Karel PTACEK

IPC分类号： H03K17/691 ,  H04B1/16 ,  H03K17/687

CPC分类号： H03K17/691 ,  H03F3/195 ,  H03F3/45179 ,  H03F2203/45306 ,  H03F2203/45621 ,  H03K17/6872 ,  H04B1/16

摘要： An illustrative embodiment of an integrated circuit configured for galvanically isolated signaling includes a transfer conductor carrying a modulated carrier signal. A floating transfer loop is electromagnetically coupled to the transfer conductor to receive the modulated carrier signal. The floating transfer loop includes a primary of a step-up transformer. A receiver is coupled to a secondary of the step-up transformer to receive the modulated carrier signal in an amplified, differential fashion, and to demodulate the modulated carrier signal to obtain a digital receive signal.

公开(公告)号：US20170281037A1

公开(公告)日：2017-10-05

申请号：US15626621

申请日：2017-06-19

申请人： T&W Engineering A/S

发明人： Preben KIDMOSE ,  Xiong ZHOU ,  Soren KILSGAARD ,  Qiang LI

IPC分类号： A61B5/0478 ,  H03F3/393 ,  H04R25/00 ,  H03F1/52 ,  H03F1/26 ,  A61B5/0408 ,  H03G3/20

CPC分类号： A61B5/0478 ,  A61B5/04004 ,  A61B5/0408 ,  A61B5/6803 ,  A61B5/6817 ,  A61B2562/0209 ,  H03F1/26 ,  H03F1/523 ,  H03F3/393 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/271 ,  H03F2203/45306 ,  H03G3/20 ,  H04R25/353 ,  H04R25/505 ,  H04R2225/43 ,  H04R2225/67

摘要： An active electrode has an electrode for sensing an electric potential and generating an input signal, and a shield placed near the electrode but being electric insulated from the electrode. An integrated amplifier (10) has an input connected to the at least one electrode for receiving the input signal, and providing a buffered path outputting a buffered output signal. The shield being connected to the output of the integrated amplifier to actively drive the electrical potential of the shield, thereby providing an active shielding of the electrode. The buffered path includes a first mixer (11) in front of the integrated amplifier for frequency shifting the input signal from a basic frequency range to a higher frequency range, and a second mixer (12) on the output of the integrated amplifier for frequency shifting the amplified signal from the higher frequency range back to the basic frequency range. The active electrode may be used for recording EEG signals.

公开(公告)号：US09628031B2

公开(公告)日：2017-04-18

申请号：US14643640

申请日：2015-03-10

申请人： QUALCOMM Incorporated

发明人： Ojas Mahendra Choksi ,  Bin Fan ,  Bassel Hanafi

IPC分类号： H03F3/45 ,  H03F1/56 ,  H03F1/32 ,  H03F1/34 ,  H03F3/193 ,  H03F3/195 ,  H04B1/525

CPC分类号： H03F1/565 ,  H03F1/3211 ,  H03F1/347 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45071 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/301 ,  H03F2200/451 ,  H03F2200/54 ,  H03F2203/21112 ,  H03F2203/45306 ,  H03F2203/45318 ,  H03F2203/45386 ,  H03F2203/45562 ,  H03F2203/45616 ,  H03F2203/45621 ,  H04B1/525

摘要： An apparatus includes: first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal; and a transformer including a primary winding and first and second secondary windings, the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors.

公开(公告)号：US20170040951A1

公开(公告)日：2017-02-09

申请号：US14913466

申请日：2015-03-16

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Daniele Mastantuono ,  Sven Mattisson

IPC分类号： H03F1/26 ,  H03F3/45 ,  H03F1/48 ,  H03F3/60 ,  H03F3/193 ,  H03F1/02

CPC分类号： H03F1/26 ,  H03F1/0205 ,  H03F1/3211 ,  H03F1/483 ,  H03F3/193 ,  H03F3/45179 ,  H03F3/607 ,  H03F2200/06 ,  H03F2200/294 ,  H03F2200/333 ,  H03F2200/451 ,  H03F2203/45306 ,  H03F2203/45318 ,  H04B1/12

摘要： An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (MCG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (MCG1) further having a first source (112) coupled to the first input (102). A second transistor (MCS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (MCS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (MCS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (MCS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (MCG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (MCG2) further having a fourth source (132) coupled to the second input (104). A first load (ZL1) is coupled between the first output (106) and a second voltage rail (136). A second load (ZL2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (MCG1) is substantially equal to transconductance of the fourth transistor (MCG2), within ±5%, and transconductance of the second transistor (MCS1) is substantially equal to transconductance of the third transistor (MCS2), within ±5%.

公开(公告)号：US09543916B2

公开(公告)日：2017-01-10

申请号：US14745261

申请日：2015-06-19

申请人： Project FT, Inc.

发明人： Farbod Aram

IPC分类号： H03F3/191 ,  H03G1/00 ,  H03F1/32 ,  H03F3/45

CPC分类号： H03G1/0029 ,  H03F1/0205 ,  H03F1/26 ,  H03F1/3205 ,  H03F1/565 ,  H03F3/193 ,  H03F3/21 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/4521 ,  H03F2200/213 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/72 ,  H03F2200/75 ,  H03F2203/45306 ,  H03F2203/45481 ,  H03G1/0005

摘要： An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

摘要翻译： 公开了一种有源器件及其使用的电路。 在一方面，有源器件包括具有漏极，栅极和体的n型晶体管和具有漏极，栅极和体的p型晶体管。 n型晶体管和p型晶体管包括公共源极。 该器件包括耦合在n型晶体管的栅极和p型晶体管的栅极之间的第一电容器，耦合在n型晶体管的漏极和p型晶体管的漏极之间的第二电容器，以及第三电容器 电容器耦合在大部分n型晶体管和大部分p型晶体管之间。 有源器件具有较高的击穿电压，较小的存储器和陷波均匀的谐波信号。

公开(公告)号：US09537457B2

公开(公告)日：2017-01-03

申请号：US14629793

申请日：2015-02-24

申请人： Intel IP Corporation

发明人： Vadim Issakov ,  Konrad Hirsch ,  Herbert Stockinger ,  Harald Doppke

IPC分类号： H03F3/26 ,  H03F1/02

CPC分类号： H03F3/265 ,  H03F1/0216 ,  H03F1/0233 ,  H03F1/0272 ,  H03F1/0283 ,  H03F1/08 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/3001 ,  H03F3/45179 ,  H03F2200/111 ,  H03F2200/121 ,  H03F2200/216 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/72 ,  H03F2203/30027 ,  H03F2203/30063 ,  H03F2203/30081 ,  H03F2203/45018 ,  H03F2203/45032 ,  H03F2203/45091 ,  H03F2203/45156 ,  H03F2203/45236 ,  H03F2203/45268 ,  H03F2203/45278 ,  H03F2203/45306 ,  H03F2203/45318 ,  H03F2203/45511 ,  H03F2203/45544 ,  H03F2203/45554 ,  H03F2203/45562

摘要： An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.

摘要翻译： 放大器工作以通过具有第一晶体管类型的第一晶体管和具有不同于第一晶体管类型的第二晶体管类型的第二晶体管的推挽级的推挽级在输出端提供高输出阻抗。 第一晶体管和第二晶体管以共栅配置耦合。 第一晶体管和第二晶体管通过耦合到输入端的电容器短路在一起，并且共享公共电流路径作为具有宽带输入匹配的推挽电流重用共栅低噪声放大器。

公开(公告)号：US20160248390A1

公开(公告)日：2016-08-25

申请号：US14629793

申请日：2015-02-24

申请人： Intel IP Corporation

发明人： Vadim Issakov ,  Konrad Hirsch ,  Herbert Stockinger ,  Harald Doppke

IPC分类号： H03F3/26 ,  H03F1/02

CPC分类号： H03F3/265 ,  H03F1/0216 ,  H03F1/0233 ,  H03F1/0272 ,  H03F1/0283 ,  H03F1/08 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/3001 ,  H03F3/45179 ,  H03F2200/111 ,  H03F2200/121 ,  H03F2200/216 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/72 ,  H03F2203/30027 ,  H03F2203/30063 ,  H03F2203/30081 ,  H03F2203/45018 ,  H03F2203/45032 ,  H03F2203/45091 ,  H03F2203/45156 ,  H03F2203/45236 ,  H03F2203/45268 ,  H03F2203/45278 ,  H03F2203/45306 ,  H03F2203/45318 ,  H03F2203/45511 ,  H03F2203/45544 ,  H03F2203/45554 ,  H03F2203/45562

摘要： An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.

摘要翻译： 放大器工作以通过具有第一晶体管类型的第一晶体管和具有不同于第一晶体管类型的第二晶体管类型的第二晶体管的推挽级的推挽级在输出端提供高输出阻抗。 第一晶体管和第二晶体管以共栅配置耦合。 第一晶体管和第二晶体管通过耦合到输入端的电容器短路在一起，并且共享公共电流路径作为具有宽带输入匹配的推挽电流重用共栅低噪声放大器。

公开(公告)号：US09385661B1

公开(公告)日：2016-07-05

申请号：US14621417

申请日：2015-02-13

申请人： Realtek Semiconductor Corp.

发明人： Chia-Liang (Leon) Lin

IPC分类号： H03F3/45 ,  H03F1/02 ,  H03F1/56 ,  H03F3/16 ,  H03F3/68 ,  H03G3/30

CPC分类号： H03G3/30 ,  H03F1/0261 ,  H03F1/26 ,  H03F3/45179 ,  H03F2200/372 ,  H03F2203/45306 ,  H03F2203/45334 ,  H03F2203/45356

摘要： In one embodiment, a circuit comprising a passive input network of an input impedance configured to couple an input voltage to a first circuit node; an adaptive current source configured to output an adaptive bias current to the first circuit node; a cascode device controlled by a control voltage and configured to receive a sum current from the first circuit node and output an output current to a second circuit node; and a load network of a load impedance configured to provide termination to the second circuit node, wherein the adaptive bias current is dynamically adapted to track a deterministic noise component in the input voltage.

摘要翻译： 在一个实施例中，包括被配置为将输入电压耦合到第一电路节点的输入阻抗的无源输入网络的电路; 自适应电流源，被配置为向所述第一电路节点输出自适应偏置电流; 由控制电压控制并被配置为从第一电路节点接收和电流并将输出电流输出到第二电路节点的共源共用器件; 以及被配置为向所述第二电路节点提供终端的负载阻抗的负载网络，其中所述自适应偏置电流被动态地适于跟踪所述输入电压中的确定性噪声分量。