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    Buffering apparatus and method
    3.
    发明授权
    Buffering apparatus and method 有权
    缓冲装置及方法

    公开(公告)号：US08890615B2

    公开(公告)日：2014-11-18

    申请号：US14084107

    申请日：2013-11-19

    Applicant: Knowles Electronics, LLC

    Inventor： Steven E. Boor

    IPC: H03F3/16 ,  H03F1/56 ,  H03F3/50

    CPC classification number: H03F1/56 ,  H03F3/16 ,  H03F3/505 ,  H03F2200/54

    Abstract: The output impedance of an amplifier is substantially matched to an input impedance of a receiver using a buffer circuit. The buffer circuit includes a primary transistor and a secondary transistor. A first back gate terminal of the primary transistor is coupled to a second back gate terminal of the secondary transistor and the primary transistor is configured to have an output for the buffer circuit. An input signal is received from the amplifier at a gate terminal of the secondary transistor. The first back gate terminal of the primary transistor is responsively driven independently from the output of the buffer circuit to effectively adjust a transconductance of the primary transistor and substantially match an output impedance of the amplifier with an input impedance of the receiver.

    Abstract translation: 放大器的输出阻抗基本上与使用缓冲电路的接收机的输入阻抗匹配。 缓冲电路包括初级晶体管和次级晶体管。 初级晶体管的第一背栅极端子耦合到次级晶体管的第二背栅极端子，并且初级晶体管被配置为具有用于缓冲电路的输出。 在二级晶体管的栅极端子处从放大器接收输入信号。 主晶体管的第一背栅极端子独立于缓冲电路的输出而被响应地驱动，以有效地调节初级晶体管的跨导，并且基本上使放大器的输出阻抗与接收器的输入阻抗匹配。

    Amplifier circuit having first amplifying section and second amplifying section
    4.
    发明授权
    Amplifier circuit having first amplifying section and second amplifying section 有权
    放大器电路具有第一放大部分和第二放大部分

    公开(公告)号：US07876161B2

    公开(公告)日：2011-01-25

    申请号：US12688070

    申请日：2010-01-15

    Applicant: Daisuke Yamazaki

    Inventor： Daisuke Yamazaki

    IPC: H03F1/52

    CPC classification number: H03F1/526 ,  H03F1/223 ,  H03F2200/444 ,  H03F2200/54

    Abstract: An amplifier circuit includes a first amplifying section for amplifying a signal, and a second amplifying section for amplifying the signal amplified by the first amplifying section. A capacitive element connects the output of the first amplifying section to the input of the second amplifying section. When power is applied to the amplifier circuit, a bypass circuit causes the electric current flowing from a first power supply toward the input of the second amplifying section through the first amplifying section and the capacitive element to be bypassed to a second power supply.

    Abstract translation: 放大器电路包括用于放大信号的第一放大部分和用于放大由第一放大部分放大的信号的第二放大部分。 电容元件将第一放大部分的输出连接到第二放大部分的输入。 当对放大器电路施加电力时，旁路电路通过第一放大部分将电流从第一电源流向第二放大部分的输入，并且电容元件被旁路至第二电源。

    OFFSET CANCELLATION FOR DC ISOLATED NODES
    5.
    发明申请
    OFFSET CANCELLATION FOR DC ISOLATED NODES 有权
    DC隔离节点偏移消除

    公开(公告)号：US20100171554A1

    公开(公告)日：2010-07-08

    申请号：US12349011

    申请日：2009-01-06

    Applicant: Justin M. Schauer ,  Robert David Hopkins ,  Robert J. Drost

    Inventor： Justin M. Schauer ,  Robert David Hopkins ,  Robert J. Drost

    IPC: H03F3/45

    CPC classification number: H03F3/45179 ,  H03F1/0261 ,  H03F3/45475 ,  H03F3/45973 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/54 ,  H03F2200/541 ,  H03F2203/45101 ,  H03F2203/45212 ,  H03F2203/45518 ,  H03F2203/45524 ,  H03F2203/45528 ,  H04B5/0031

    Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

    Abstract translation: 在与输入到放大器的数据信号直流隔离的高性能放大器的输入上开发的浮动电压上的偏移电压通过在输入节点和预定电位之间连接高电阻元件而被消除，在邻近通信系统中特别有用，其中两个 芯片通过在两个芯片中共同形成的电容或电感耦合电路连接。 电阻元件可以是连接在节点和期望偏置电压之间的截止MOS晶体管，或者其栅极和漏极连接到电位的MOS晶体管。 可以将多个偏置电压分配给所有接收器，并由多路复用器本地选择以应用于接收器的一个或两个输入节点。 当电阻元件与数据速率相比具有长时间常数或电阻元件是非线性时，接收器输出也可以用作预定电位。

    Method and apparatus for biasing a floating node in an integrated circuit
    6.
    发明授权
    Method and apparatus for biasing a floating node in an integrated circuit 有权
    用于偏置集成电路中的浮动节点的方法和装置

    公开(公告)号：US07750709B1

    公开(公告)日：2010-07-06

    申请号：US11651221

    申请日：2007-01-05

    Applicant: Justin M. Schauer ,  Robert D. Hopkins

    Inventor： Justin M. Schauer ,  Robert D. Hopkins

    IPC: H03H11/26

    CPC classification number: H03F3/45475 ,  H03F2200/537 ,  H03F2200/54 ,  H03F2203/45101 ,  H03F2203/45542

    Abstract: One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.

    Abstract translation: 本发明的一个实施例提供了一种偏置集成电路内的浮动节点的系统。 在操作期间，系统首先识别集成电路内的浮动节点以进行偏置。 然后系统确定期望的偏置电压。 接下来，系统将低功率偏置源耦合到浮动节点以提供期望的偏置电压，其中浮动节点在偏置期间被偏置而不停止通过浮动节点的数据传输。

    High speed amplifier with controllable amplification and output impedance and comparator using the same
    7.
    发明授权
    High speed amplifier with controllable amplification and output impedance and comparator using the same 失效
    具有可控放大和输出阻抗的高速放大器和使用相同的比较器

    公开(公告)号：US07741908B2

    公开(公告)日：2010-06-22

    申请号：US11783112

    申请日：2007-04-05

    Applicant: Atsushi Furuta

    Inventor： Atsushi Furuta

    IPC: H03F3/45

    CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2200/54 ,  H03F2200/78 ,  H03F2203/45138 ,  H03F2203/45171 ,  H03F2203/45418 ,  H03F2203/45616 ,  H03F2203/45641 ,  H03F2203/45642 ,  H03F2203/45652 ,  H03F2203/45686

    Abstract: In an amplifier including first and second power supply terminals, first and second output terminals, a first load connected between the first power supply terminal and the first output terminal, a second load connected between the first power supply terminal and the second output terminal, a constant current source connected to the second power supply terminal, a first transistor connected between the first output terminal and the constant current source, a control terminal of the first transistor being adapted to receive an input voltage, and a second transistor connected between the second output terminal and the constant current source, a control terminal of the second transistor being adapted to receive a reference voltage, an amplification and output impedance switching circuit is connected between the first and second output terminals, so that the amplifier and output impedance switching circuit controls an amplification and output impedance of the amplifier in accordance with a control signal.

    Abstract translation: 在包括第一和第二电源端子的放大器中，第一和第二输出端子连接在第一电源端子和第一输出端子之间的第一负载，连接在第一电源端子和第二输出端子之间的第二负载， 连接到第二电源端子的恒流源，连接在第一输出端子和恒流源之间的第一晶体管，第一晶体管的控制端子适于接收输入电压，第二晶体管连接在第二输出端 端子和恒流源，第二晶体管的控制端子适于接收参考电压，放大和输出阻抗切换电路连接在第一和第二输出端子之间，使得放大器和输出阻抗切换电路控制一个 放大器的放大和输出阻抗按照a 控制信号。

    Enhancement-depletion Darlington device
    9.
    发明授权
    Enhancement-depletion Darlington device 有权
    增强耗尽达林顿装置

    公开(公告)号：US07439805B1

    公开(公告)日：2008-10-21

    申请号：US11422928

    申请日：2006-06-08

    Applicant: Kevin W. Kobayashi

    Inventor： Kevin W. Kobayashi

    IPC: H03F3/16

    CPC classification number: H03F3/211 ,  H01L28/10 ,  H03F1/34 ,  H03F1/342 ,  H03F3/505 ,  H03F2200/456 ,  H03F2200/492 ,  H03F2200/54 ,  H03F2200/93 ,  H03F2203/5042

    Abstract: An apparatus comprising a Darlington transistor pair comprising a first transistor and a second transistor. The first transistor may have a gate configured to receive an input signal. The second transistor may have a gate coupled to a source of the first transistor. The Darlington transistor pair may be configured to generate an output signal at a drain of the first transistor and a drain of the second transistor in response to the input signal. The first transistor may be implemented as an enhancement mode device and the second transistor may be implemented as a depletion mode device.

    Abstract translation: 一种包括具有第一晶体管和第二晶体管的达林顿晶体管对的装置。 第一晶体管可以具有被配置为接收输入信号的栅极。 第二晶体管可以具有耦合到第一晶体管的源极的栅极。 达林顿晶体管对可以被配置为响应于输入信号在第一晶体管的漏极和第二晶体管的漏极处产生输出信号。 第一晶体管可以被实现为增强模式器件，并且第二晶体管可以被实现为耗尽型器件。

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