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公开(公告)号：US10063193B2
公开(公告)日：2018-08-28
申请号：US15483067
申请日：2017-04-10
CPC分类号： H03F1/3205 , H03F1/3217 , H03F3/185 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/3022 , H03F2200/03 , H03F2200/297 , H03F2200/301 , H03F2200/303 , H03F2200/312 , H03F2200/351 , H03F2200/391 , H03F2200/417 , H03F2200/421 , H03F2200/426 , H03F2200/432 , H03F2200/441 , H03F2200/444 , H03F2200/459
摘要： A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting. To reduce distortion and more particularly, total harmonic distortion (THD), the amplifier output stage includes a substantially linear circuit configured to provide a bidirectional current sink for residual currents from the load occurring during at least part of each dead time interval.
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公开(公告)号：US09985633B1
公开(公告)日：2018-05-29
申请号：US15263201
申请日：2016-09-12
IPC分类号： H03K5/08 , H03K19/018
CPC分类号： H03K19/01806 , H03F3/3069 , H03F3/45071 , H03F2200/441 , H03K5/08 , H03K19/00307 , H03K19/017509 , H03M1/1295
摘要： A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.
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公开(公告)号：US20170302232A1
公开(公告)日：2017-10-19
申请号：US15483067
申请日：2017-04-10
CPC分类号： H03F1/3205 , H03F1/3217 , H03F3/185 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/3022 , H03F2200/03 , H03F2200/297 , H03F2200/301 , H03F2200/303 , H03F2200/312 , H03F2200/351 , H03F2200/391 , H03F2200/417 , H03F2200/421 , H03F2200/426 , H03F2200/432 , H03F2200/441 , H03F2200/444 , H03F2200/459
摘要： A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting. To reduce distortion and more particularly, total harmonic distortion (THD), the amplifier output stage includes a substantially linear circuit configured to provide a bidirectional current sink for residual currents from the load occurring during at least part of each dead time interval.
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4.发明申请公开(公告)号：US20170272674A1
公开(公告)日：2017-09-21
申请号：US15453372
申请日：2017-03-08
发明人： Yusuke TOKUNAGA
CPC分类号： H04N5/378 , G11C27/026 , H03F1/223 , H03F3/3028 , H03F2200/27 , H03F2200/441 , H03F2203/30084 , H03F2203/30117 , H03K5/08 , H03M1/1245 , H03M3/458 , H04N5/374
摘要： An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.
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公开(公告)号：US20170141748A1
公开(公告)日：2017-05-18
申请号：US15241035
申请日：2016-08-18
申请人： MEDIATEK INC.
发明人： Lai-Ching Lin , Ming-Da Tsai
IPC分类号： H03G3/30 , H03F3/193 , H03K5/1532 , H03F3/21
CPC分类号： H03G3/3042 , H03F1/223 , H03F1/523 , H03F3/193 , H03F3/195 , H03F3/21 , H03F3/245 , H03F3/45179 , H03F3/45475 , H03F3/72 , H03F2200/108 , H03F2200/153 , H03F2200/18 , H03F2200/228 , H03F2200/234 , H03F2200/258 , H03F2200/301 , H03F2200/393 , H03F2200/435 , H03F2200/441 , H03F2200/451 , H03F2200/462 , H03F2200/471 , H03F2200/477 , H03F2200/481 , H03F2200/498 , H03F2200/555 , H03F2200/75 , H03F2200/78 , H03K5/1532
摘要： The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.
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公开(公告)号：US20150381125A1
公开(公告)日：2015-12-31
申请号：US14613455
申请日：2015-02-04
发明人： Kelvin Jian Wen , Mei Yang , Zheng Hua Song , Xian Xiong , Cristiano Meroni
CPC分类号： H03F3/187 , H03F3/45475 , H03F3/45941 , H03F2200/03 , H03F2200/441 , H03F2203/45138 , H03F2203/45418 , H03F2203/45424 , H03F2203/45528 , H03F2203/45541
摘要： A power amplifier includes a clamping circuit configured to provide a clamped voltage from a power supply; an amplifier pair having first inputs coupled to the clamping circuit, second inputs and an output for providing an amplified signal; and a biasing circuit coupled between the clamping circuit and the second inputs. The biasing circuit is configured to adjust input bias voltages of the amplifier pair such that the bias voltage of the output of the amplifier pair varies proportionally to a change of the power supply.
摘要翻译： 功率放大器包括被配置为提供来自电源的钳位电压的钳位电路; 放大器对，其具有耦合到所述钳位电路的第一输入，第二输入和用于提供放大信号的输出; 以及耦合在所述钳位电路和所述第二输入之间的偏置电路。 偏置电路被配置为调整放大器对的输入偏置电压，使得放大器对的输出的偏置电压与电源的变化成比例地变化。
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7.发明授权公开(公告)号：US08396089B2
公开(公告)日：2013-03-12
申请号：US12359653
申请日：2009-01-26
IPC分类号： H04J3/02
CPC分类号： H03F3/68 , H03F1/52 , H03F3/45475 , H03F2200/165 , H03F2200/261 , H03F2200/441 , H03F2203/45138
摘要： An acquisition device and corresponding method for operating the acquisition system are provided. Generally, during operation a plurality of input signals are filtered and multiplexed. The multiplexed input signals are then applied to an amplifier stage; however, when a clamping condition for the amplifier stage occurs, a buffer is switched into a signal path between a multiplexer and an amplifier stage so as to generally reduce the current draw on the input filters.
摘要翻译： 提供了一种用于操作采集系统的采集装置和相应方法。 通常，在操作期间，对多个输入信号进行滤波和多路复用。 然后将复用的输入信号施加到放大器级; 然而，当发生用于放大器级的钳位条件时，缓冲器被切换到多路复用器和放大器级之间的信号路径，以便通常减少输入滤波器上的电流消耗。
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公开(公告)号：US20120281325A1
公开(公告)日：2012-11-08
申请号：US13514632
申请日：2010-11-25
申请人： Rolf Reber , Patrick Schuh
发明人： Rolf Reber , Patrick Schuh
IPC分类号： H02H9/02
CPC分类号： H03G11/04 , H03F1/523 , H03F2200/211 , H03F2200/441 , H03F2200/66
摘要： A limiting circuit has a signal input and a signal output for limiting an output signal that is present at the signal output and that can be fed to a further circuit connected to the output of the limiting circuit. A voltage connection for feeding a bias voltage and a transistor are present, wherein the gate connection of the transistor is connected to the voltage connection by means of a first matching circuit and to the signal input by means of a second matching circuit.
摘要翻译： 限制电路具有信号输入和信号输出，用于限制存在于信号输出端的输出信号，并且可以馈送到连接到限制电路的输出端的另一个电路。 存在用于馈送偏置电压和晶体管的电压连接，其中晶体管的栅极连接通过第一匹配电路连接到电压连接，并通过第二匹配电路连接到信号输入。
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公开(公告)号：US08279001B2
公开(公告)日：2012-10-02
申请号：US13173307
申请日：2011-06-30
IPC分类号： H03G3/20
CPC分类号： H03F3/3076 , H03F1/0227 , H03F3/187 , H03F3/68 , H03F2200/03 , H03F2200/102 , H03F2200/33 , H03F2200/411 , H03F2200/441 , H03F2200/504 , H03F2200/78
摘要： Several push-pull linear hybrid class H amplifiers are disclosed. A split power rail provides a positive supply rail and a negative supply rail in response to a power supply control voltage. A push-pull amplifier stage is powered by the positive and negative supply rails. The amplifier stage receives an input signal and provides a corresponding amplified output signal. A power supply control circuit provides the power supply control voltage in response to the smaller of the positive and negative supply rails, and the input signal.
摘要翻译： 公开了几个推挽线性混合级H放大器。 分流电源轨提供正电源轨和负电源轨以响应电源控制电压。 推挽放大器级由正负电源电源供电。 放大器级接收输入信号并提供相应的放大输出信号。 电源控制电路响应于正负电源轨和输入信号中的较小者提供电源控制电压。
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公开(公告)号：US20100289580A1
公开(公告)日：2010-11-18
申请号：US12454320
申请日：2009-05-15
申请人： David Standley , Laurent Blanquart
发明人： David Standley , Laurent Blanquart
IPC分类号： H03F3/45
CPC分类号： H03F1/523 , H03F3/45192 , H03F2200/441 , H03F2203/45636
摘要： An operational trans-conductance amplifier circuit having a voltage clamp circuit. The clamp circuit utilizes low area and power overhead, has a sharp clamp characteristic, and little degradation in the small-signal DC gain at the “knee” of the clamp characteristic. The clamp circuit includes a comparator circuit and a current control circuit. The amplifier and clamp circuits may further include a clamp voltage generator circuit.
摘要翻译： 一种具有电压钳位电路的运行的跨导放大器电路。 钳位电路利用低面积和功率开销，具有尖锐的钳位特性，并且在钳位特性的“拐点”处的小信号DC增益几乎没有劣化。 钳位电路包括比较器电路和电流控制电路。 放大器和钳位电路还可以包括钳位电压发生器电路。
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