公开(公告)号：US5661066A

公开(公告)日：1997-08-26

申请号：US965967

申请日：1991-04-02

申请人： Toyoki Takemoto ,  Haruyasu Yamada ,  Tsutomu Fujita ,  Tadao Komeda

发明人： Toyoki Takemoto ,  Haruyasu Yamada ,  Tsutomu Fujita ,  Tadao Komeda

IPC分类号： H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L29/8605 ,  H01L29/93 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0233 ,  H01L21/8222 ,  H01L27/0244 ,  H01L27/0647 ,  H01L29/8605 ,  H01L29/93

摘要： In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.

摘要翻译： 在包括IIL和高频npn双极晶体管的集成电路中，其具有用于其反相npn输出晶体管的深p型基极区45，电路元件如电阻器部分R，电容器部分C，二极管部分D 并且隔离交叉连接部分Cr设置有与IIL中的p型区域45同时形成的深P型区域54,54'，65'，71和82，从而可靠性 的电路元件及其特性得到改善，从而进一步提高了制造成品率。

公开(公告)号：US4505766A

公开(公告)日：1985-03-19

申请号：US491543

申请日：1983-05-04

申请人： Shuzo Nagumo ,  Setsuo Ogura ,  Yukinori Kitamura

发明人： Shuzo Nagumo ,  Setsuo Ogura ,  Yukinori Kitamura

IPC分类号： H01L27/04 ,  H01L21/22 ,  H01L21/331 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L29/73 ,  H01L29/93 ,  H01L21/20

CPC分类号： H01L21/2205 ,  H01L21/74 ,  H01L27/0244 ,  H01L27/0647 ,  H01L27/0805 ,  H01L29/93 ,  Y10S438/901

摘要： A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

摘要翻译： 半导体器件具有第一导电类型的扩散层，其延伸到第二导电类型的掩埋层，其以从外延生长的第二导电类型的半导体层的表面的一部分延伸的方式形成 通过第二导电类型的掩埋层的第一导电类型的半导体衬底。 半导体结电容由第一导电类型的扩散层和第二导电类型的掩埋层形成，并且控制要引入到第二导电类型的掩埋层中的杂质的浓度。

公开(公告)号：US4412142A

公开(公告)日：1983-10-25

申请号：US219824

申请日：1980-12-24

申请人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

发明人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

IPC分类号： H01L27/02 ,  H01L27/082 ,  H03K17/28 ,  H03K17/615 ,  H03K17/795 ,  H01L27/04 ,  H03K19/091

CPC分类号： H03K17/795 ,  H01L27/0244 ,  H01L27/0821 ,  H01L27/0825 ,  H03K17/28 ,  H03K17/615

摘要： An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

摘要翻译： 公开了一种包含由低电压半导体器件控制的高电压半导体器件的集成电路，包括其制造方法。 与用于制造离散高压功率晶体管的工艺相比，能够在同一芯片上实现复杂逻辑功能的低电压器件在制造过程中只需一个简单的额外步骤。 植入低电压器件的加工过程不会显着降低与分立功率晶体管相关的原始能力。 描述了侧向显影和垂直显影的装置。 集成电路将I2L逻辑与功率达林顿晶体管相结合。 大面积离子注入允许在一个衬底上制造低压和高压器件。 所得到的集成电路允许通过简单或复杂的控制功能来控制多个负载。

公开(公告)号：US5066602A

公开(公告)日：1991-11-19

申请号：US295380

申请日：1989-01-10

申请人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

发明人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L27/092

CPC分类号： H01L27/0244 ,  H01L21/74 ,  H01L21/761 ,  H01L21/82285 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/0922 ,  Y10S148/009 ,  Y10S148/151

摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

公开(公告)号：US4567501A

公开(公告)日：1986-01-28

申请号：US563887

申请日：1983-12-22

申请人： Takeshi Fukuda

发明人： Takeshi Fukuda

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/07 ,  H01L29/73 ,  H01L29/8605 ,  H01L27/04

CPC分类号： H01L27/0244 ,  H01L21/8226 ,  H01L27/075 ,  H01L29/7304 ,  H01L29/8605

摘要： An I.sup.2 L semiconductor device in which a p-type buried layer is formed on an n.sup.+ type silicon substrate by diffusion of boron, an epitaxial n-type layer is grown on the p-type buried layer, a p.sup.+ type region is formed in a ring shape to surround the epitaxial n-type layer with the bottom of the p.sup.+ region reaching to the p-type buried layer, an n-type resistor layer is formed in the epitaxial n-type layer by diffusion of phosphorus, and connections for electrodes are formed by diffusion of n.sup.+ type impurities in such a manner that the connections make contact with the resistor layer.

摘要翻译： 一种I2L半导体器件，其中通过硼的扩散在n +型硅衬底上形成p型掩埋层，在p型掩埋层上生长外延n型层，在p型掩模层中形成p +型区域 形状以围绕外延n型层，其中p +区的底部到达p型掩埋层，通过磷的扩散在外延n型层中形成n型电阻层，并且电极的连接为 通过使n +型杂质以连接方式与电阻层接触的方式形成。

公开(公告)号：US4543499A

公开(公告)日：1985-09-24

申请号：US366784

申请日：1982-04-08

申请人： Kenji Kaneko ,  Minoru Nagata ,  Makoto Furihata ,  Setsuo Ogura ,  Takahiro Okabe ,  Mitsuya Sato

发明人： Kenji Kaneko ,  Minoru Nagata ,  Makoto Furihata ,  Setsuo Ogura ,  Takahiro Okabe ,  Mitsuya Sato

IPC分类号： H01L21/8226 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H03K19/091 ,  H03K19/092

CPC分类号： H01L27/0244 ,  H01L27/06

摘要： A semiconductor integrated circuit includes low voltage operation circuitries such as I.sup.2 L and high voltage operation circuitries operating at a higher voltage than the low voltage operation circuitries. Both of the low and high voltage operation circuitries are implemented in a single semiconductor chip in coexistence with each other. The low voltage operation circuitries are disposed in constant current paths in the high voltage operation circuitries so that the currents once used by the high voltage operation circuits are utilized again by the low voltage operation circuitries. Power dissipation of the whole integrated circuit is thus reduced significantly.

摘要翻译： 半导体集成电路包括低电压操作电路，例如I2L和高电压工作电路，工作电压高于低电压工作电路。 低电压和高电压操作电路都可以在单个半导体芯片中实现，彼此共存。 低电压工作电路在高电压工作电路中以恒定电流通路设置，使得高电压操作电路一度使用的电流被低压操作电路再利用。 因此整个集成电路的功耗显着降低。

公开(公告)号：US4536784A

公开(公告)日：1985-08-20

申请号：US541445

申请日：1983-10-13

申请人： Shuzo Nagumo ,  Setsuo Ogura ,  Yukinori Kitamura

发明人： Shuzo Nagumo ,  Setsuo Ogura ,  Yukinori Kitamura

IPC分类号： H01L27/04 ,  H01L21/22 ,  H01L21/331 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L29/73 ,  H01L29/93 ,  H01L29/92

CPC分类号： H01L21/2205 ,  H01L21/74 ,  H01L27/0244 ,  H01L27/0647 ,  H01L27/0805 ,  H01L29/93 ,  Y10S438/901

摘要： A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

摘要翻译： 半导体器件具有第一导电类型的扩散层，其延伸到第二导电类型的掩埋层，其以从外延生长的第二导电类型的半导体层的表面的一部分延伸的方式形成 通过第二导电类型的掩埋层的第一导电类型的半导体衬底。 半导体结电容由第一导电类型的扩散层和第二导电类型的掩埋层形成，并且控制要引入到第二导电类型的掩埋层中的杂质的浓度。

公开(公告)号：US5280188A

公开(公告)日：1994-01-18

申请号：US989455

申请日：1992-12-08

申请人： Hiroshi Iwasaki

发明人： Hiroshi Iwasaki

IPC分类号： H01L21/225 ,  H01L21/8226 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/02 ,  H01L29/06 ,  H01L29/45 ,  H01L29/732 ,  H01L29/72 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L21/2257 ,  H01L21/8226 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/0244 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/7325 ,  H01L2924/0002

摘要： A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The impurity layer is formed of a polycide layer formed of a polysilicon layer doped with an impurity and a metal silicide layer laminated on the polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, or a metal silicide layer.

摘要翻译： 半导体器件包括制造在单个晶片上的双极晶体管和IIL元件。 双极晶体管的发射极区域通过使形成在其中的基极区域形成的杂质层的杂质扩散而形成。 杂质层由多晶硅层形成，该多晶硅层由掺杂有杂质的多晶硅层和层叠在多晶硅层上的金属硅化物层，多晶硅层和难熔金属层的叠层或金属硅化物层构成。

公开(公告)号：US5144408A

公开(公告)日：1992-09-01

申请号：US730518

申请日：1991-07-12

申请人： Hiroshi Iwasaki

发明人： Hiroshi Iwasaki

IPC分类号： H01L21/225 ,  H01L21/8226 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/02 ,  H01L29/06 ,  H01L29/45 ,  H01L29/732

CPC分类号： H01L29/0692 ,  H01L21/2257 ,  H01L21/8226 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/0244 ,  H01L29/456 ,  H01L29/7325 ,  H01L2924/0002

摘要： A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The impurity layer is formed of a polycide layer formed of a polysilicon layer doped with an impurity and a metal silicide layer laminated on the polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, or a metal silicide layer.

摘要翻译： 半导体器件包括制造在单个晶片上的双极晶体管和IIL元件。 双极晶体管的发射极区域通过使形成在其中的基极区域形成的杂质层的杂质扩散而形成。 杂质层由多晶硅层形成，该多晶硅层由掺杂有杂质的多晶硅层和层叠在多晶硅层上的金属硅化物层，多晶硅层和难熔金属层的叠层或金属硅化物层构成。

公开(公告)号：US4502201A

公开(公告)日：1985-03-05

申请号：US326278

申请日：1981-12-01

申请人： Akira Muramatsu

发明人： Akira Muramatsu

IPC分类号： H01L21/8226 ,  H01L21/331 ,  H01L21/762 ,  H01L21/8228 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L21/76

CPC分类号： H01L21/82285 ,  H01L21/76205 ,  H01L27/0244 ,  H01L27/0828

摘要： The invention discloses a semiconductor integrated circuit device characterized in that an inverse transistor element portion and a normal transistor element portion are formed in a common semiconductor layer and are separated from each other by an oxide layer penetrating said semiconductor layer in the direction of its thickness. In particular, in order to attain improved characteristics for the respective devices, the semiconductor layer of the inverse transistor element portion is thinner than the semiconductor layer of the normal transistor element portion.

摘要翻译： 本发明公开了一种半导体集成电路器件，其特征在于，在公共半导体层中形成反向晶体管元件部分和正常晶体管元件部分，并且通过在其厚度方向穿过所述半导体层的氧化物层彼此分离。 特别地，为了获得各器件的特性，逆晶体管元件部分的半导体层比普通晶体管元件部分的半导体层薄。