公开(公告)号：US06531890B1

公开(公告)日：2003-03-11

申请号：US08459570

申请日：1995-06-02

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz

IPC分类号： H03K19177

CPC分类号： H03K19/177 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.

摘要翻译： 可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。 可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。 然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。 可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到 可编程选择逻辑宏单元。 具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。 每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。

公开(公告)号：US5811987A

公开(公告)日：1998-09-22

申请号：US740948

申请日：1996-11-05

申请人： Benjamin Howard Ashmore, Jr. ,  Jeffery Mark Marshall ,  Bryon Irwin Moyer ,  John David Porter ,  Nicholas A. Schmitz ,  Bradley A. Sharpe-Geisler

发明人： Benjamin Howard Ashmore, Jr. ,  Jeffery Mark Marshall ,  Bryon Irwin Moyer ,  John David Porter ,  Nicholas A. Schmitz ,  Bradley A. Sharpe-Geisler

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/173 ,  H03K19/177 ,  H03K19/21 ,  H03K7/38

CPC分类号： H03K3/037 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17772 ,  H03K19/215 ,  H03K3/0375 ,  H03K3/356156

摘要： A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.

摘要翻译： 复合非常高密度可编程逻辑器件中的可编程逻辑块的块时钟和初始化电路为可编程逻辑块中的元件生成多个块时钟信号和块初始化信号。 块时钟和初始化电路包括块时钟发生器电路和块初始化电路。 块时钟发生器电路以多个乘积项和多个时钟信号作为输入信号接收第一组乘积项。 响应于输入信号，块时钟发生器电路在多个块时钟线上产生输出信号。 块初始化电路接收多个乘积项中的第二组乘积项作为输入信号。 响应于输入信号，块初始化电路在块初始化线上产生多个输出信号。

公开(公告)号：US4475280A

公开(公告)日：1984-10-09

申请号：US450687

申请日：1982-12-17

申请人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

发明人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

IPC分类号： H01L27/02 ,  H01L27/082 ,  H03K17/28 ,  H03K17/60 ,  H03K17/795 ,  H01L21/80

CPC分类号： H01L27/0244 ,  H01L27/0821 ,  H01L27/0825 ,  H03K17/28 ,  H03K17/60 ,  H03K17/795

摘要： An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

摘要翻译： 公开了一种包含由低电压半导体器件控制的高电压半导体器件的集成电路，包括其制造方法。 与用于制造离散高压功率晶体管的工艺相比，能够在同一芯片上实现复杂逻辑功能的低电压器件在制造过程中只需一个简单的额外步骤。 植入低电压器件的加工过程不会显着降低与分立功率晶体管相关的原始能力。 描述了侧向显影和垂直显影的装置。 集成电路将I2L逻辑与功率达林顿晶体管相结合。 大面积离子注入允许在一个衬底上制造低压和高压器件。 所得到的集成电路允许通过简单或复杂的控制功能来控制多个负载。

公开(公告)号：US06753696B1

公开(公告)日：2004-06-22

申请号：US10338619

申请日：2003-01-08

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz

IPC分类号： H03K19173

CPC分类号： H03K19/177 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.

摘要翻译： 可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。 可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。 然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。 可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到 可编程选择逻辑宏单元。 具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。 每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。

公开(公告)号：US5521529A

公开(公告)日：1996-05-28

申请号：US459960

申请日：1995-06-02

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz ,  Bryon I. Moyer

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz ,  Bryon I. Moyer

IPC分类号： H03K19/177 ,  H03K19/082 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.

摘要翻译： 一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。 层次结构的最低层次与所有更高层次是独立的。 类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。 第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。 第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三级别信号路径利用第三级，第二级和第一层次级资源。 第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。

公开(公告)号：US4412142A

公开(公告)日：1983-10-25

申请号：US219824

申请日：1980-12-24

申请人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

发明人： Louis J. Ragonese ,  Nicholas A. Schmitz ,  Saverio F. Bevacqua ,  King Owyang

IPC分类号： H01L27/02 ,  H01L27/082 ,  H03K17/28 ,  H03K17/615 ,  H03K17/795 ,  H01L27/04 ,  H03K19/091

CPC分类号： H03K17/795 ,  H01L27/0244 ,  H01L27/0821 ,  H01L27/0825 ,  H03K17/28 ,  H03K17/615

摘要： An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

摘要翻译： 公开了一种包含由低电压半导体器件控制的高电压半导体器件的集成电路，包括其制造方法。 与用于制造离散高压功率晶体管的工艺相比，能够在同一芯片上实现复杂逻辑功能的低电压器件在制造过程中只需一个简单的额外步骤。 植入低电压器件的加工过程不会显着降低与分立功率晶体管相关的原始能力。 描述了侧向显影和垂直显影的装置。 集成电路将I2L逻辑与功率达林顿晶体管相结合。 大面积离子注入允许在一个衬底上制造低压和高压器件。 所得到的集成电路允许通过简单或复杂的控制功能来控制多个负载。

公开(公告)号：US5869981A

公开(公告)日：1999-02-09

申请号：US479872

申请日：1995-06-06

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US5225719A

公开(公告)日：1993-07-06

申请号：US699427

申请日：1991-05-13

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US5128871A

公开(公告)日：1992-07-07

申请号：US490817

申请日：1990-03-07

申请人： Nicholas A. Schmitz

发明人： Nicholas A. Schmitz

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： G06F17/5054

摘要： Programmable logic device design software is provided for allocating specific resources in a programmable logic device having a multiplicity of programmable logic blocks interconnected by a programmable switch matrix to logic equations in a user logic design. In particular, a resource allocation means for fitting a logic design to a multiplicity of programmable logic blocks with limited interconnectivity between the modules is provided. The resource allocation means requires minimal programmable logic device resources to achieve the allocation of resources within the programmable logic device to the user logic design. The resource allocation means employs block partitioning means and resource assignment means to map user logic to a programmable logic device (PLD) having multiple programmable AND fixed OR arrays interconnected by a programmable switch matrix, i.e., allocate the PLD resources to the user logic.

公开(公告)号：US4245177A

公开(公告)日：1981-01-13

申请号：US974351

申请日：1978-12-29

申请人： Nicholas A. Schmitz

发明人： Nicholas A. Schmitz

IPC分类号： H01F29/14 ,  H01F38/10 ,  H02M7/5383 ,  H05B41/288 ,  H05B37/00 ,  H05B39/00 ,  H05B41/14

CPC分类号： H02M7/53835 ,  H01F29/14 ,  H01F38/10 ,  H05B41/2885 ,  H01F2029/143 ,  H01F2038/026 ,  Y02B70/1441 ,  Y10S315/05 ,  Y10S315/07

摘要： A dc to ac inverter for operating a gaseous discharge lamp through pre-ignition, arc stabilization, warm-up and final run states is disclosed. The arrangement comprises a transformer and a pair of transistors connected for alternate conduction in a self-oscillating configuration in which turn off occurs at a predetermined flux level in each conduction period. The flux limit is used to preclude excess current drain during warm-up when the lamp resistance is at a minimum. A capacitor is provided, resonant at a harmonic of the inverter output waveform for producing the enhanced output voltage required for pre-ignition. The capacitor also helps to maintain a higher harmonic content during warm-up, enhancing the effective ballasting reactance during that period in relation to that during final run operation. A shift of the oscillating frequency of the inverter from pre-ignition to final run operation further enhances inverter operation.

摘要翻译： 公开了一种用于通过预点火，电弧稳定，预热和最终运行状态操作气体放电灯的直流到交流逆变器。 该装置包括变压器和一对晶体管，其连接用于以自激振荡配置交替传导，其中在每个导通周期中以预定的通量水平发生关断。 当灯电阻最小时，通量限制用于防止预热期间的过大电流消耗。 提供电容器，以逆变器输出波形的谐波谐振，以产生预点火所需的增强的输出电压。 电容器还有助于在预热期间保持较高的谐波含量，从而在最后的运行过程中增强了有效的镇流电抗。 变频器的振荡频率从预启动转移到最终运行操作进一步增强了逆变器的运行。