公开(公告)号：US20180190869A1

公开(公告)日：2018-07-05

申请号：US15740410

申请日：2016-07-01

Applicant: LG INNOTEK CO., LTD.

Inventor： Shuhei MATSUDA

IPC: H01L33/36 ,  H01L33/60 ,  H01L33/62 ,  H01L33/64 ,  H01L23/00

CPC classification number: H01L33/36 ,  H01L24/16 ,  H01L24/42 ,  H01L24/48 ,  H01L25/167 ,  H01L33/60 ,  H01L33/62 ,  H01L33/64 ,  H01L33/647 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/83411 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83466 ,  H01L2224/83469 ,  H01L2224/83471 ,  H01L2224/83481 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/85466 ,  H01L2224/85469 ,  H01L2224/85471 ,  H01L2224/85481 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2224/45099

Abstract: A light emitting device disclosed in an embodiment includes: a light emitting chip including a plurality of semiconductor layers and first and second electrodes under the plurality of semiconductor layers; a first lead frame disposed under a first electrode of the light emitting chip; a second lead frame disposed under a second electrode of the light emitting chip; a protective chip disposed between the first and second lead frames and electrically connected to the first and second electrodes; and a reflective member disposed on a periphery of the light emitting chip and the first and second lead frames.

公开(公告)号：US20070296081A1

公开(公告)日：2007-12-27

申请号：US11768919

申请日：2007-06-27

Applicant: Kye Nam Lee ,  Young Jin Park ,  Hyun Kyu Yang ,  Yoo Ran Kim

Inventor： Kye Nam Lee ,  Young Jin Park ,  Hyun Kyu Yang ,  Yoo Ran Kim

IPC: H01L23/48

CPC classification number: H01L24/12 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/056 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85466 ,  H01L2224/85481 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/013

Abstract: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.

Abstract translation: 公开了一种半导体封装及其制造方法。 半导体封装包括半导体芯片，其包括设置在半导体衬底的上侧的预定区域上的金属焊盘，其中形成用于制造半导体元件的元件结构，以及连接到金属焊盘的凸块电极; 以及设置在半导体芯片的除凸起电极的上表面以外的整个表面上的钝化膜。 因此，可以避免在传统的倒装芯片接合中使用的环氧底层填充工艺的困难，以及由于使用模塑复合工艺和焊球工艺而导致的复杂性和高成本。 由于在现有的晶片级封装中在半导体芯片的侧面上没有钝化膜，所以也可以防止半导体芯片的侧面的损坏。

公开(公告)号：US20140252640A1

公开(公告)日：2014-09-11

申请号：US14061198

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Keun Kwak

IPC: H01L23/49

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/5381 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/48681 ,  H01L2224/48684 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/48769 ,  H01L2224/48781 ,  H01L2224/48784 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85466 ,  H01L2224/85469 ,  H01L2224/85476 ,  H01L2224/85481 ,  H01L2224/85484 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/0715 ,  H01L2924/066 ,  H01L2924/07001 ,  H01L2924/0635 ,  H01L2924/00

Abstract: A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive wires are formed between the first semiconductor chips and the first finger electrodes. A second tower including second semiconductor chips is formed on the substrate. Second conductive wires are formed between the second semiconductor chips and the second finger electrodes. The external terminals include a first group connected to the first finger electrodes and configuring a channel, and a second group connected to the second finger electrodes, and configuring another channel. The first finger electrodes are formed on the third quadrant, and the second finger electrodes are formed on the first quadrant.

Abstract translation: 包括内部互连的基板，第一和第二指状电极，并且具有第一至第四象限。 外部端子形成在基板上并通过内部互连连接到第一和第二指状电极。 包括第一半导体芯片的第一塔形成在基板上。 第一导电线形成在第一半导体芯片和第一指状电极之间。 包括第二半导体芯片的第二塔形成在基板上。 在第二半导体芯片和第二指状电极之间形成第二导线。 外部端子包括连接到第一指状电极并构成通道的第一组以及连接到第二指状电极的第二组，并且配置另一个通道。 第一指状电极形成在第三象限上，第二指状电极形成在第一象限上。

公开(公告)号：US20120074456A1

公开(公告)日：2012-03-29

申请号：US13304510

申请日：2011-11-25

Applicant: Hongboem JIN

Inventor： Hongboem JIN

IPC: H01L33/62 ,  H01L33/64

CPC classification number: H01L33/642 ,  H01L33/486 ,  H01L33/62 ,  H01L33/647 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85409 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/85466 ,  H01L2224/85469 ,  H01L2224/85471 ,  H01L2224/85476 ,  H01L2224/85481 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light emitting device package is disclosed. The disclosed light emitting device package includes a body comprising a cavity, and a recess formed at a bottom surface of the body, first and second lead frames mounted in the body, and a light source electrically connected with the first and second lead frames, wherein at least one of the first and second lead frames has a heat sink which is extended from a portion of the first or the second lead frames, and is disposed in the recess. The body includes a first coupler formed on at least a portion of the body. The heat sink includes a second coupler, to which the first coupler is coupled.

Abstract translation: 公开了一种发光器件封装。 所公开的发光器件封装包括：主体，其包括空腔，形成在主体的底表面处的凹部，安装在主体中的第一引线框架和第二引线框架以及与第一引线框架和第二引线框架电连接的光源，其中 第一引线框架和第二引线框架中的至少一个具有从第一引线框架或第二引线框架的一部分延伸的散热器，并且设置在凹部中。 主体包括形成在主体的至少一部分上的第一联接器。 散热器包括第二耦合器，第一耦合器耦合到第二耦合器。

公开(公告)号：US20090215259A1

公开(公告)日：2009-08-27

申请号：US12417644

申请日：2009-04-03

Applicant: Kye Nam LEE ,  Young Jin PARK ,  Hyun Kyu YANG ,  Yoo Ran KIM

Inventor： Kye Nam LEE ,  Young Jin PARK ,  Hyun Kyu YANG ,  Yoo Ran KIM

IPC: H01L21/768

CPC classification number: H01L24/12 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/056 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85466 ,  H01L2224/85481 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/013

Abstract: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.

Abstract translation: 公开了一种半导体封装及其制造方法。 半导体封装包括半导体芯片，其包括设置在半导体衬底的上侧的预定区域上的金属焊盘，其中形成用于制造半导体元件的元件结构，以及连接到金属焊盘的凸块电极; 以及设置在半导体芯片的除凸起电极的上表面以外的整个表面上的钝化膜。 因此，可以避免在传统的倒装芯片接合中使用的环氧底层填充工艺的困难，以及由于使用模塑复合工艺和焊球工艺而导致的复杂性和高成本。 由于在现有的晶片级封装中在半导体芯片的侧面上没有钝化膜，所以也可以防止半导体芯片的侧面的损坏。