公开(公告)号：US09214200B2

公开(公告)日：2015-12-15

申请号：US13635028

申请日：2011-02-26

申请人： Michael Bucher ,  John Wilson

发明人： Michael Bucher ,  John Wilson

IPC分类号： G06F1/04 ,  G06F1/12 ,  H04L7/00 ,  G06F5/06 ,  G11C7/10 ,  G06F1/03 ,  G06F13/42 ,  G06F1/06 ,  H04B3/32 ,  H04L25/02 ,  G06F13/38

CPC分类号： G11C7/1051 ,  G06F1/0342 ,  G06F1/04 ,  G06F1/06 ,  G06F13/38 ,  G06F13/4243 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  H04B3/32 ,  H04L7/0008 ,  H04L25/026 ,  H04L25/0264

摘要： A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit. The receiver circuit samples the encoded output signal in response to the nominal timing signal to generate even and odd sampled data signals. Complementary timing signals can be transmitted through transmission lines on opposite sides of the encoded output signal to provide crosstalk cancellation.

摘要翻译： 一种系统包括通过传输线耦合在一起的发射机电路和接收机电路。 发射机电路产生早期定时信号，标称定时信号和延迟定时信号。 多路复用器电路基于数据信号在早期和晚期定时信号之间进行选择，以产生对数据信号进行编码的编码输出信号。 标称定时信号和编码的输出信号通过传输线传输到接收器电路。 接收器电路响应于标称定时信号对编码的输出信号进行采样，以产生偶数和奇数采样数据信号。 互补定时信号可以通过编码输出信号相对侧的传输线传输，以提供串扰消除。

公开(公告)号：US08060327B2

公开(公告)日：2011-11-15

申请号：US11863281

申请日：2007-09-28

申请人： Makoto Kurosawa

发明人： Makoto Kurosawa

IPC分类号： G01R13/00

CPC分类号： G06F1/0342

摘要： There is provided a waveform generator for generating an analog signal, including a data changing section which changes an input data sequence, which is to be modulated to the signal which the waveform generator should generate, to generate an after-change data sequence such that an initial phase and a final phase of the signal to be obtained by FSK modulation are continuous, a waveform generating section which generates basic waveform data representing a waveform corresponding to the signal obtained by subjecting the after-change data sequence to FSK modulation, and an output section which outputs the signal repeating the waveform represented by the basic waveform data.

摘要翻译： 提供了一种用于产生模拟信号的波形发生器，其包括将要调制的输入数据序列改变为波形发生器应产生的信号的数据改变部分，以产生改变后的数据序列， 通过FSK调制获得的信号的初始相位和最后相位是连续的，波形生成部分生成表示对应于后变化数据序列进行FSK调制获得的信号的波形的基本波形数据，以及输出 输出重复由基本波形数据表示的波形的信号。

公开(公告)号：US07889812B2

公开(公告)日：2011-02-15

申请号：US11442195

申请日：2006-05-26

申请人： David S. Trager ,  Mitchell Reid

发明人： David S. Trager ,  Mitchell Reid

IPC分类号： H03K9/00 ,  H03D3/00 ,  H03M1/66

CPC分类号： G06F1/0353 ,  G06F1/0335 ,  G06F1/0342

摘要： A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.

摘要翻译： 接收器（1000）包括直接数字频率合成器（DDFS）（700）和第一（1040）和第二（1042）混频器。 DDFS（700）具有用于提供第一本地振荡器信号的第一输出和用于提供与第一本地振荡器信号的正交关系偏移相位偏移的第二本地振荡器信号的第二输出。 第一混频器（1040）具有用于接收射频（RF）信号的第一输入端，用于接收第一本机振荡器信号的第二输入端和用于提供另一频率的同相信号的输出端。 第二混频器（1042）具有用于接收RF信号的第一输入端，用于接收第二本机振荡器信号的第二输入端和用于以另一频率提供正交信号的输出端。 DDFS（700）可以使用存储正弦​​波形的部分的第一（702）和第二（704）存储器以及支持相位偏移的额外存储器（706,708）来实现。

公开(公告)号：US07805273B2

公开(公告)日：2010-09-28

申请号：US12176429

申请日：2008-07-21

申请人： Makoto Kurosawa

发明人： Makoto Kurosawa

IPC分类号： G01R35/02

CPC分类号： G06F1/0342

摘要： Provided is a waveform generating apparatus that generates analog signal based on fundamental waveform data including a predetermined number of samples, including: phase difference calculating section that calculates phase difference between the initial phase and final phase of a signal resulting from FSK-modulating, based on first set of modulation frequencies, input data sequence to be modulated onto a signal that the waveform generating apparatus generates; frequency calculating section that calculates correction frequency corresponding to quotient of dividing, by the predetermined number of samples, residue of dividing the phase difference by 2π; waveform producing section that produces fundamental waveform data representing a waveform corresponding to a signal resulting from FSK-modulating the input data sequence based on second set of modulation frequencies obtained by subtracting the correction frequency from the modulation frequencies in the first set; and output section that outputs a signal repeating the waveform represented by the fundamental waveform data.

摘要翻译： 提供了一种波形发生装置，其基于包括预定数量的采样的基本波形数据生成模拟信号，该波形发生装置包括：基于由FSK调制产生的信号的初始相位和最终相位之间的相位差计算的相位差计算部， 第一组调制频率，要调制到波形发生装置产生的信号上的输入数据序列; 频率计算部分，计算对应于除数的校正频率的预定数量的样本，将相位差除以2的残差; 波形产生部，其基于从所述第一组中的调制频率减去校正频率得到的第二组调制频率，生成表示对应于由所述输入数据序列进行FSK调制而得到的信号的波形的波形数据; 以及输出部，其输出重复由基本波形数据表示的波形的信号。

公开(公告)号：US07570120B1

公开(公告)日：2009-08-04

申请号：US11820268

申请日：2007-06-18

申请人： Benjamin Esposito

发明人： Benjamin Esposito

IPC分类号： H03L7/085 ,  H03K19/177

CPC分类号： H03K19/17732 ,  G06F1/0342

摘要： A multichannel numerically controlled oscillator is provided. The multichannel numerically controlled oscillator has a dual port memory. An output function generation lookup table in the dual port memory is used to generate output functions for the numerically controlled oscillator. A first channel of output is generated based on a first address signal that is presented on a first port of the dual port memory. A second channel of output is generated based on a second address signal that is presented on a second port of the dual port memory. First and second phase accumulators may be used to produce the address signals for the first and second ports of the dual port memory, respectively. The phase accumulators may each contain a register, an adder, and a feedback path. The registers in the phase accumulators and the dual port memory may handle signals at the clock rate of the output channels.

摘要翻译： 提供多通道数控振荡器。 多通道数控振荡器具有双端口存储器。 双端口存储器中的输出函数生成查找表用于产生数控振荡器的输出功能。 基于在双端口存储器的第一端口上呈现的第一地址信号来产生第一输出通道。 基于在双端口存储器的第二端口上呈现的第二地址信号来产生第二输出通道。 第一和第二相位累加器可以分别用于产生双端口存储器的第一和第二端口的地址信号。 相位累加器可以各自包含寄存器，加法器和反馈路径。 相位累加器和双端口存储器中的寄存器可以以输出通道的时钟速率处理信号。

公开(公告)号：US20090157783A1

公开(公告)日：2009-06-18

申请号：US12237832

申请日：2008-09-25

申请人： Seok SEO ,  Min Joung SHEEN ,  Gweon Do JO

发明人： Seok SEO ,  Min Joung SHEEN ,  Gweon Do JO

IPC分类号： G06F1/02

CPC分类号： G06F1/0353 ,  G06F1/0342

摘要： A numerically-controlled oscillator (NCO) and an operating method of the NCO are provided. According to the NCO and the operating method of the NCO, it is possible to reduce the size of a lookup table memory by using a lookup table, which stores a plurality of phase compensation values for different phases obtained by using a cosine function or a sine function. Thus, it is possible to easily calculate cosine and sine addresses and cosine and sine signs and to quickly provide a cosine phase compensation signal and a sine phase compensation signal.

摘要翻译： 提供数控振荡器（NCO）和NCO的操作方法。 根据NCO和NCO的操作方法，可以通过使用查找表来减小查找表存储器的大小，该查找表存储通过使用余弦函数或正弦来获得的不同相位的多个相位补偿值 功能。 因此，可以容易地计算余弦和正弦地址，余弦和正弦符号并且快速提供余弦相位补偿信号和正弦相位补偿信号。

公开(公告)号：US06781473B1

公开(公告)日：2004-08-24

申请号：US10242947

申请日：2002-09-13

申请人： John S Chiu ,  Roger Stenerson ,  Sricharan Kasetti ,  WeiMin Zhang

发明人： John S Chiu ,  Roger Stenerson ,  Sricharan Kasetti ,  WeiMin Zhang

IPC分类号： H03B2100

CPC分类号： G06F1/0353 ,  G06F1/0342

摘要： Method and apparatus for generating sinusoidal signals in quadrature. A numerically controlled oscillator includes a phase accumulator configured to generate a periodic multi-bit signal at a given frequency; a first memory configured to store an octant of a sinusoidal waveform; a second memory configured to store a complementary octant of the sinusoidal waveform; and a control circuit, responsive to at least a portion of the phase accumulator signal and coupled to the first and second memories, the control circuit configured to access the first and second memories in parallel and construct respective sine and cosine waves at the given frequency.

摘要翻译： 用于产生正交正弦信号的方法和装置。 数控振荡器包括相位累加器，其被配置为以给定频率产生周期性多位信号; 配置为存储正弦波形的八分圆的第一存储器; 第二存储器，被配置为存储所述正弦波形的互补八分圆; 以及控制电路，响应于所述相位累加器信号的至少一部分并且耦合到所述第一和第二存储器，所述控制电路被配置为并行访问所述第一和第二存储器并且以给定频率构造相应的正弦和余弦波。

公开(公告)号：US6118680A

公开(公告)日：2000-09-12

申请号：US322726

申请日：1999-05-28

申请人： Kenneth Andrew Wallace ,  Gueorgui I. Mantov ,  Jon Drew Karnes ,  John Roller

发明人： Kenneth Andrew Wallace ,  Gueorgui I. Mantov ,  Jon Drew Karnes ,  John Roller

IPC分类号： G06F1/03 ,  H02M7/48 ,  H02M7/493 ,  H02M7/00

CPC分类号： H02M7/493 ,  G06F1/0342

摘要： Methods and apparatus are disclosed for achieving load balance between parallel inverters in an AC power supply. Load balancing reduces undesirable cross conduction current between the parallel inverters. Load balancing and the resulting reduction in cross conduction current are achieved without the need for common control circuitry between the parallel inverters. Thus, the single-fault protection offered by redundant parallel inverters is not compromised by the disclosed load balancing techniques.

摘要翻译： 公开了用于实现交流电源中的并联逆变器之间的负载平衡的方法和装置。 负载平衡可降低并联逆变器之间的不必要的交叉传导电流。 在不需要并联逆变器之间的公共控制电路的情况下，实现负载平衡和所导致的交叉传导电流的减小。 因此，冗余并联逆变器提供的单故障保护不受所公开的负载均衡技术的影响。

公开(公告)号：US5363443A

公开(公告)日：1994-11-08

申请号：US163968

申请日：1993-12-08

申请人： Norman W. Petty

发明人： Norman W. Petty

IPC分类号： G06F1/03 ,  H04Q1/444 ,  H04Q1/46 ,  H04M3/00

CPC分类号： G06F1/0342 ,  H04Q1/444 ,  H04Q1/46

摘要： Sine waves are generated by a port circuit processor of a telephone switching office by accessing a look-up table stored in a memory associated with the port circuit processor. Entries in the look-up table are accessed by using table steps or .DELTA.'s which correspond to the frequencies of the sine waves to be generated. The table steps or .DELTA.'s are changed for different sine wave frequencies and may be changed each bit period. Whether changed or not, a first fractional portion of the table step or .DELTA. for the previous frequency is combined with a second fractional portion of the table step or .DELTA. for the current frequency with the first and second fractional portions adding up to one. In this way, an X sample per second data stream, X equaling the base sample rate of the look-up table, that precisely matches a Y bits per second rate, Y equaling the transmission rate of the data stream, is generated.

摘要翻译： 通过访问存储在与端口电路处理器相关联的存储器中的查找表，由电话交换局的端口电路处理器产生正弦波。 通过使用与要生成的正​​弦波的频率相对应的表格步骤或DELTA来访问查找表中的条目。 对于不同的正弦波频率，台阶或DELTA被改变，并且可以在每个位周期改变。 无论是否改变，表步骤的第一小数部分或前一个频率的DELTA与表步骤的第二小数部分或当前频率的DELTA组合，第一和第二小数部分加起来一个。 以这种方式，生成等于数据流的传输速率的与每秒Y比特精确匹配的等于每个查询表的基本采样率的每秒X个样本数据流X。

公开(公告)号：US5255288A

公开(公告)日：1993-10-19

申请号：US648758

申请日：1991-01-31

申请人： Masaki Ichihara

发明人： Masaki Ichihara

IPC分类号： H03H17/02 ,  H03H17/00 ,  H04L25/03 ,  H04L27/12 ,  H03K7/06

CPC分类号： G06F1/0353 ,  H04L25/03834 ,  G06F1/0342

摘要： In order to effectively reduce a memory size of each of two memories provided in an arrangement for converting a binary input data into the corresponding inphase and quadrature signals, a memory output controller and a sequential logic are provided. The memory output controller includes two polarity control circuits and two input data selectors. The two polarity control circuits are respectively coupled to the two memories, while the two input data selectors are preceded by and coupled to both of the two polarity control circuits. Each of the two polarity control circuits reverses the polarity of the output of the associated memory according to the output of the sequential logic. On the other hand, each of the two input data selectors is arranged to selectively acquire the outputs of the two polarity control circuits depending on the output of the sequential logic.