公开(公告)号：US08924449B2

公开(公告)日：2014-12-30

申请号：US13145558

申请日：2009-12-29

申请人： Wei Luo

发明人： Wei Luo

IPC分类号： G06F1/02 ,  G06F1/03

CPC分类号： G06F1/0335

摘要： A method for implementing variable symbol rate, presetting counters M and N, and M=1, N=0, f being the preset output symbol rate, fs being the frequency of input clock, the method comprises: triggering to judge whether N×f is greater than M×fs at the rising edge of the input clock, if it is, letting the counter M add 1 and outputting a clock pulse; else further judging whether the value of the counter N is equal to fs−1; when N=fs−1, letting the counter N return to 0, and waiting for the next rising edge of the input clock; when N≠fs−1, waiting for the next rising edge of the input clock after letting the counter N add 1; letting the output clock pulse be the system clock, controlling the data to be output to set the symbol rate output.

摘要翻译： 一种用于实现可变符号速率，预置计数器M和N以及M = 1，N = 0，f为预设输出符号率的方法，fs是输入时钟的频率，该方法包括：触发判断N×f 在输入时钟的上升沿大于M×fs，如果是，则使计数器M加1并输出时钟脉冲; 否则进一步判断计数器N的值是否等于fs-1; 当N = fs-1时，使计数器N返回0，并等待输入时钟的下一个上升沿; 当N≠fs-1时，等待计数器N加1后输入时钟的下一个上升沿; 将输出时钟脉冲作为系统时钟，控制要输出的数据以设置符号速率输出。

公开(公告)号：US06614813B1

公开(公告)日：2003-09-02

申请号：US09238762

申请日：1999-01-28

申请人： Peter A. Dudley ,  Bert L. Tise

发明人： Peter A. Dudley ,  Bert L. Tise

IPC分类号： H04J304

CPC分类号： G06F1/0335

摘要： A synthesizer for generating a desired chirp signal has M parallel channels, where M is an integer greater than 1, each channel including a chirp waveform synthesizer generating at an output a portion of a digital representation of the desired chirp signal; and a multiplexer for multiplexing the M outputs to create a digital representation of the desired chirp signal. Preferably, each channel receives input information that is a function of information representing the desired chirp signal.

摘要翻译： 用于产生期望啁啾信号的合成器具有M个并行信道，其中M是大于1的整数，每个信道包括啁啾波形合成器，其在输出处产生期望啁啾信号的数字表示的一部分; 以及多路复用器，用于多路复用M个输出以产生期望的线性调频信号的数字表示。 优选地，每个通道接收作为表示所需啁啾信号的信息的函数的输入信息。

公开(公告)号：US20030063662A1

公开(公告)日：2003-04-03

申请号：US09890441

申请日：2001-07-25

申请人： Anritsu Corporation

发明人： Masaharu Uchino ,  Kazuhiko Ishibe ,  Takashi Aoki

IPC分类号： H04Q001/20 ,  H04B003/46 ,  H04B017/00

CPC分类号： G06F1/0335 ,  G06F7/584 ,  H04L1/24 ,  H04L25/03343

摘要： A wander generator has a random number signal generator unit, a filter unit, a clock generator unit, a modulator unit, and a setting unit. The random number generator unit sequentially generates random number signals comprised of a plurality of bits at a constant speed in accordance with a predetermined algorithm. The filter unit receives a random number signal sequence generated by the random number signal generator unit for filtering. The clock generator unit generates a clock signal. The modulator unit modulates the frequency of clock signal generated by the clock generator unit with a signal output from the filter unit. The setting unit applies the filter unit with a signal for setting each amplitude value of a spectrum of a signal sequence output from the filter unit.

摘要翻译： 漂移发生器具有随机数信号发生器单元，滤波器单元，时钟发生器单元，调制器单元和设置单元。 随机数发生器单元根据预定的算法顺序地以恒定速度产生由多个位组成的随机数信号。 滤波器单元接收由随机数信号发生器单元产生的用于滤波的随机数信号序列。 时钟发生器单元产生时钟信号。 调制器单元利用从滤波器单元输出的信号来调制由时钟发生器单元产生的时钟信号的频率。 设置单元对滤波器单元施加用于设置从滤波器单元输出的信号序列的频谱的每个振幅值的信号。

公开(公告)号：US06522176B1

公开(公告)日：2003-02-18

申请号：US09998836

申请日：2001-11-15

申请人： Brian M. Davis

发明人： Brian M. Davis

IPC分类号： H03B2100

CPC分类号： G06F1/0335 ,  G06F1/0342 ,  G06F2211/902

摘要： A direct digital synthesizer for generating an output signal within a frequency band. The direct digital synthesizer comprises an input section for receiving a phase differential value and generating a phase angle value. A phase-amplitude converter generates an amplitude value in response to the phase angle value. A band-shaped dither generator generates a dither value. A first combiner sums the amplitude value and the dither value to define a first combined value. A second combiner differences the amplitude value and the dither value to define a second combined value. A first digital-to-analog converter (DAC) converts the first combined value to a first analog signal. A second digital-to-analog converter (DAC) converts the second combined value to a second analog signal. An output combiner combines the first analog signal and the second analog signal to generate the output signal.

摘要翻译： 一种用于在频带内产生输出信号的直接数字合成器。 直接数字合成器包括用于接收相位差值并产生相位角值的输入部分。 相位振幅转换器响应于相位角值产生振幅值。 带状抖动发生器产生抖动值。 第一组合器将振幅值和抖动值相加以定义第一组合值。 第二组合器将振幅值和抖动值差分以限定第二组合值。 第一数模转换器（DAC）将第一组合值转换为第一模拟信号。 第二数模转换器（DAC）将第二组合值转换为第二模拟信号。 输出组合器组合第一模拟信号和第二模拟信号以产生输出信号。

公开(公告)号：US5553011A

公开(公告)日：1996-09-03

申请号：US391466

申请日：1995-02-21

申请人： Yoshio Fujita

发明人： Yoshio Fujita

IPC分类号： G10H7/00 ,  G06F1/03 ,  G10H1/043 ,  G10H1/053 ,  G10H7/02 ,  G10H7/08 ,  G10H7/12 ,  G06F1/02

CPC分类号： G06F1/0335 ,  G10H7/12 ,  G10H2250/621 ,  G10H2250/631

摘要： A waveform generating apparatus for generating waveforms which can be suitably employed in electronic musical instruments. The waveform generating apparatus calculates and generates regenerated sample data of a regenerated waveform having a desired pitch in synchronization with a constant regeneration sampling interval based on basic sample data which are sampled from a basic waveform by a predetermined basic sampling interval. The apparatus includes a phase generator, an operation mode control circuit and an interpolating circuit. The phase generator generates phase data which designates a phase of basic waveform. The operation mode control circuit supplies a calculation designating data. The interpolating circuit calculates regenerated sample data on the basis of basic sample data and phase data. Wherein, the method of the interpolation which is performed by the interpolating circuit is altered in response to calculation designating data. Thus, waveform can be regenerated accurately and with high fidelity over a wide range of pitches.

摘要翻译： 一种用于产生可以适用于电子乐器的波形的波形发生装置。 波形发生装置基于从基本波形采样预定的基本采样间隔的基本采样数据，与恒定的再生采样间隔同步地计算并产生具有所需音调的再生波形的再生样本数据。 该装置包括相位发生器，操作模式控制电路和内插电路。 相位发生器产生指定基本波形相位的相位数据。 操作模式控制电路提供计算指定数据。 内插电路根据基本样本数据和相位数据计算再生样本数据。 其中，根据计算指定数据改变由内插电路执行的内插方法。 因此，可以在宽范围的间距上以高保真度准确地再生波形。

公开(公告)号：US5521534A

公开(公告)日：1996-05-28

申请号：US492927

申请日：1995-06-21

申请人： Paul M. Elliott

发明人： Paul M. Elliott

IPC分类号： G06F1/03 ,  H03B28/00 ,  H03B1/00

CPC分类号： G06F1/0335 ,  H03B28/00

摘要： A numerically controlled oscillator (10) includes a difference engine (12) that receives a numerator signal (14) and a numerator minus denominator signal (16). The numerator signal (14) and the numerator minus denominator signal (16) represent constant input values for a desired fractional relationship between a sine wave output signal (34) and a sample clock input signal (20) of numerically controlled oscillator (10). The difference engine (12) generates a difference output signal (18) that is received by a phase adder (22) for adding either a one or a zero to a combination of the delta phase input signal (24) and a phase accumulator output signal (26). The difference engine (12) optimally distributes ones and zeros so as to minimize phase jitter in the output signal (34).

摘要翻译： 数控振荡器（10）包括接收分子信号（14）和分子负分母信号（16）的差分引擎（12）。 分子信号（14）和分子负分母信号（16）表示正弦波输出信号（34）和数控振荡器（10）的采样时钟输入信号（20）之间的期望的分数关系的恒定输入值。 差分引擎（12）产生差分输出信号（18），该差分输出信号（18）由相位加法器（22）接收，用于将一个或一个零加到增量相位输入信号（24）和相位累加器输出信号 （26）。 差分引擎（12）最佳地分配零和零以便最小化输出信号（34）中的相位抖动。

公开(公告)号：US5144571A

公开(公告)日：1992-09-01

申请号：US841784

申请日：1992-03-02

申请人： Tran Thong

发明人： Tran Thong

IPC分类号： G06F1/03

CPC分类号： G06F1/0335

摘要： A direct digital synthesizer (DDS) for generating an output periodic waveform from a stored digital waveform has a linear feedback shift register coonfigured as a counter. The linear feedback shift register is clocked by the internal reference clock of the DDS, and a predetermined output of the linear feedback shift register is detected to provide a control signal. The control signal causes the frequency or phase of the output waveform to be changed according to control parameters input to a control logic circuit. The control logic circuit preloads the new parameter vlaues into appropriate frequency/phase registers which are switched to the input of the accumulator in the DDS on the next cycle of the reference clock when the control signal is detected.

摘要翻译： 用于从存储的数字波形产生输出周期波形的直接数字合成器（DDS）具有作为计数器配置的线性反馈移位寄存器。 线性反馈移位寄存器由DDS的内部参考时钟计时，并且检测线性反馈移位寄存器的预定输出以提供控制信号。 控制信号使输出波形的频率或相位根据输入到控制逻辑电路的控制参数而改变。 控制逻辑电路将新的参数vlaues加载到适当的频率/相位寄存器中，当检测到控制信号时，它们在基准时钟的下一个周期切换到DDS中的累加器的输入。

公开(公告)号：US5053982A

公开(公告)日：1991-10-01

申请号：US310134

申请日：1989-02-14

申请人： Earl W. McCune, Jr.

发明人： Earl W. McCune, Jr.

IPC分类号： G06F1/03

CPC分类号： G06F1/0335

摘要： A synthesizer capable of generating a multiplicity of output frequency signals with 1 hertz resolution utilizing binary mathematics in a binary circuit. The apparatus includes providing to an accumulator a stable reference input signal having a frequency value of K, a defined value of 2.sup.N where N is an integer, a rollover value R equal to 2.sup.N minus the synthesizer modulus M and a desired output frequency signal having a value V selected from the range of integer values between 1 and K. The accumulator, at the rate of K, periodically increments the accumulator contents A by the value V, until the accumulated value exceeds 2.sup.N -1. The accumulator's content A is then set at the next cycle of the reference input signal K to a value of A-2.sup.N +R+V. A convertor converts the values of A into an output signal. In the preferred embodiment, the accumulator includes digital circuitry having 2.sup.N capacity and performs binary arithmetic to accomplish the accumulations.

摘要翻译： 一种能够在二进制电路中利用二进制数学产生具有1赫兹分辨率的多个输出频率信号的合成器。 该装置包括向累加器提供具有频率值K的稳定的参考输入信号，2N的定义值N，其中N是整数，翻转值R等于2N减去合成器模数M，以及期望的输出频率信号具有 值V从1到K之间的整数值的范围中选择。累加器以K的速率周期性地将累加器内容A增加值V，直到累加值超过2N-1。 然后将累加器的内容A设置在参考输入信号K的下一个周期，到A-2N + R + V的值。 转换器将A的值转换为输出信号。 在优选实施例中，累加器包括具有2N个容量的数字电路，并执行二进制运算以完成累加。

公开(公告)号：US09671817B1

公开(公告)日：2017-06-06

申请号：US15187895

申请日：2016-06-21

申请人： Raytheon Company

发明人： Michael Thielen

IPC分类号： H03L7/00 ,  G06F1/03 ,  H03K23/50

CPC分类号： G06F1/0335 ,  H03K23/502 ,  H03L7/00

摘要： Embodiments relate to an accumulator-based phase memory. An aspect includes a phase correction calculator configured to, based on receipt of a new frequency tuning word on a frequency tuning word input, determine a phase difference between the new frequency tuning word and a current frequency tuning word, and determine a product of the phase difference and a value of a counter. Another aspect includes wherein the accumulator-based phase memory determines a phase offset value based on the product of the phase difference and the value of the counter. Another aspect includes the accumulator-based phase memory further comprising a waveform generator configured to generate a waveform based on the new frequency tuning word and the phase offset value.

公开(公告)号：US08428213B2

公开(公告)日：2013-04-23

申请号：US12546738

申请日：2009-08-25

申请人： Hans Juergen Tucholski

发明人： Hans Juergen Tucholski

IPC分类号： H03D3/24

CPC分类号： H03K5/156 ,  G06F1/0335 ,  H03L7/08 ,  H03L7/0814

摘要： A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5). A comparing circuit (20) compares the period of the synthesized output signal waveform on the output terminal (4) with the period of the input signal, and a control circuit (28) produces progressively altered values of a frequency control digital word which are sequentially applied to an accumulator (11) of the direct digital synthesizer (10) in response to the comparing circuit (20), until the value of the frequency control digital word applied to the accumulator (11) is such as to produce the synthesized output signal waveform to be substantially phase and frequency locked to the phase and frequency input signal applied to the input terminal (5).

摘要翻译： 数字波形合成器（1）在单个芯片（2）上实现为单芯片集成电路，并且包括直接数字合成器（10），其在基本上相位的输出端子（4）上产生合成的输出信号波形， 频率锁定到施加到输入端子（5）的外部产生的输入信号的相位和频率。 比较电路（20）将输出端子（4）上的合成输出信号波形的周期与输入信号的周期进行比较，并且控制电路（28）产生顺序改变的频率控制数字字的值， 响应于比较电路（20），将直接数字合成器（10）的累加器（11）施加到累加器（11）的频率控制数字字的值，以产生合成输出信号 波形基本上相位和频率锁定到施加到输入端子（5）的相位和频率输入信号。