FULLY DEPLETED REGION FOR REDUCED PARASITIC CAPACITANCE BETWEEN A POLY-SILICON LAYER AND A SUBSTRATE REGION
    10.
    发明申请
    FULLY DEPLETED REGION FOR REDUCED PARASITIC CAPACITANCE BETWEEN A POLY-SILICON LAYER AND A SUBSTRATE REGION 有权
    完全覆盖的区域,用于降低聚硅层和基片区域之间的平行电容

    公开(公告)号:US20160145093A1

    公开(公告)日:2016-05-26

    申请号:US14942824

    申请日:2015-11-16

    IPC分类号: B81B3/00 B81C1/00 H04R23/00

    摘要: A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.

    摘要翻译: 可以使用完全耗尽区域来减少具有多晶硅层的电子器件中的多对衬底寄生电容。 当完全耗尽区域至少部分地位于电子器件下方时,在完全耗尽区域和衬底区域之间形成附加的寄生电容。 该额外的寄生电容与电子器件的多晶硅层与掺杂区域之间的第一寄生电容串联耦合。 第一寄生电容和附加寄生电容的串联组合导致电子器件的寄生电容体验的总体减小。 该结构可以在电子器件的侧面上包括两个掺杂区域,以基于掺杂区域和衬底区域中掺杂剂的横向相互作用形成完全耗尽区域。