公开(公告)号：US20240404583A1

公开(公告)日：2024-12-05

申请号：US18676782

申请日：2024-05-29

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Masakazu KAKUMU ,  Koji SAKUI ,  Nozomu HARADA

IPC: G11C11/4096 ,  H01L23/528 ,  H10B12/00

Abstract: In a semiconductor memory device, an n-type semiconductor layer is formed on a p-type semiconductor region on a substrate, a p-type first semiconductor layer having a columnar shape and concave top surface extends vertically from part of the n-type semiconductor layer, the p-type first semiconductor layer and n-type semiconductor layer are partially covered with an insulating layer, a first gate insulating layer is placed in contact with the p-type first semiconductor layer, a first gate conductor layer is placed in contact with the first gate insulating layer, and a second gate insulating layer, a second gate conductor layer, and an access transistor with an n+ layer provided on both sides are installed along a surface of the p-type first semiconductor layer.

公开(公告)号：US12159923B2

公开(公告)日：2024-12-03

申请号：US17740656

申请日：2022-05-10

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Nozomu Harada ,  Koji Sakui

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: Provided on a substrate 1 are an N+ layer connecting to a source line SL, a first Si pillar as a P+ layer standing in an upright position along the vertical direction, and a second Si pillar as a P layer. An N+ layer connecting to a bit line BL is provided on the second Si pillar. A first gate insulating layer is provided so as to surround the first Si pillar, and a second gate insulating layer is provided so as to surround the second Si pillar. A first gate conductor layer connecting to a plate line PL is provided so as to surround the first insulating layer, and a second gate conductor layer connecting to a word line WL is provided so as to surround the second insulating layer. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data write operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region, and a data erase operation for removing the holes from the channel region.

公开(公告)号：US20240389297A1

公开(公告)日：2024-11-21

申请号：US18660471

申请日：2024-05-10

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Nozomu HARADA ,  Masakazu KAKUMU ,  Koji SAKUI

IPC: H10B12/00

Abstract: A first impurity region that is connected to a first semiconductor layer, a first gate insulating layer that is in contact with the first semiconductor layer, a first gate conductor layer that is in contact with the first gate insulating layer, a second semiconductor layer that is in contact with a top of the first semiconductor layer, a second and third impurity regions that are along both edges of the second semiconductor layer in a horizontal direction, a second gate insulating layer that covers the second semiconductor layer between the second and third impurity regions, and a second gate conductor layer that is in contact with a top of the second gate insulating layer are included. Positions of both edges of the second semiconductor layer in a second direction perpendicular to a first direction are inside positions of both edges of the first semiconductor layer in a plan view.

公开(公告)号：US12127385B2

公开(公告)日：2024-10-22

申请号：US17565738

申请日：2021-12-30

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H01L21/311

CPC classification number: H10B10/12 ,  H01L21/76816 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/31116 ,  H01L21/31144

Abstract: In formation of an SRAM cell, a band-shaped contact hole C3 is formed that does not overlap, in plan view. N+ layers 32a, 32c, 32d, and 32f formed on and at outer peripheries of the top portions of Si pillars 6a, 6c, 6d, and 6f, that partly overlaps W layers 33b and 33e on P+ layers 32b and 32e connected to the top portions of Si pillars 6b and 6e, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layers 32b and 32e through the contact hole C3 is formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.

公开(公告)号：US12125520B2

公开(公告)日：2024-10-22

申请号：US18194960

申请日：2023-04-03

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Masakazu Kakumu ,  Koji Sakui ,  Nozomu Harada

IPC: G11C11/40 ,  G11C11/409 ,  H10B12/00

CPC classification number: G11C11/409 ,  H10B12/20

Abstract: A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.

公开(公告)号：US20240334675A1

公开(公告)日：2024-10-03

申请号：US18616472

申请日：2024-03-26

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Koji SAKUI ,  Yoshihisa Iwata ,  Masakazu Kakumu ,  Nozomu Harada

IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

Abstract: In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity region and a second impurity region at both ends of the semiconductor base, and at least two gate conductor layers. The first impurity region is connected to a source line, the second impurity region to a bit line, one of the two gate conductor layers to a selection gate line, and the other to a plate line. Voltages applied to these lines are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have three-valued logic storage data. A sense amplifier circuit performs determination in an order of logic storage data with a large number of holes in the hole group.

公开(公告)号：US12096611B2

公开(公告)日：2024-09-17

申请号：US17718573

申请日：2022-04-12

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Koji Sakui ,  Nozomu Harada

IPC: H01L21/02 ,  G11C11/4097 ,  H10B12/00

CPC classification number: H10B12/20 ,  G11C11/4097

Abstract: A memory device includes a plurality of memory cells each including a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a memory write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a memory erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, a voltage of the word line changes from a first voltage to a second voltage that is higher than the first voltage, and a voltage of the bit lines subsequently change from a third voltage to a fourth voltage that is higher than the third voltage to perform a memory read operation of reading to the bit lines, pieces of storage data in a plurality of semiconductor base materials selected by the word line.

公开(公告)号：US12096608B2

公开(公告)日：2024-09-17

申请号：US17493251

申请日：2021-10-04

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada ,  Yisuo Li

IPC: H10B10/00 ,  H10K59/121

CPC classification number: H10B10/12 ,  H10K59/121 ,  G09G2300/0819 ,  G09G2300/0823

Abstract: In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.

公开(公告)号：US20240196591A1

公开(公告)日：2024-06-13

申请号：US18537189

申请日：2023-12-12

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Masakazu KAKUMU ,  Koji SAKUI ,  Nozomu HARADA

IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

Abstract: A memory device includes an n-layer 3a formed on a p-layer 1 of a substrate; an n-layer 3b extending in a vertical direction with a columnar p-layer 4 placed thereon; an insulating layer 2; a gate insulating layer 5; a gate conductor layer 22; an insulating layer 6; and a MOSFET made up of a p-layer 8, a gate insulating layer 9, n+ layers 7a and 7b, and a gate conductor layer 10. The n+ layers 7a and 7b, the gate conductor layers 5 and 10, and n-layer 3a are connected to a source line, bit line, plate line, and word line, and control line, respectively. Data retention operation is performed by controlling voltages applied to the respective layers to hold positive hole groups generated in the MOSFET, and data erase operation is performed to remove positive holes accumulated in the p-layer.

公开(公告)号：US20240194250A1

公开(公告)日：2024-06-13

申请号：US18537121

申请日：2023-12-12

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Nozomu HARADA ,  Koji SAKUI

IPC: G11C11/4096 ,  G11C5/06 ,  G11C16/14 ,  G11C16/26 ,  H10B12/00

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C16/14 ,  G11C16/26 ,  H10B12/20

Abstract: A two-stage dynamic flash memory is formed as follows. An N+ layer 20 is formed in a pillar-shaped semiconductor layer 12, which stands on an N+ layer 2a, by performing a heat treatment, thereby producing an effect of forcing a donor impurity out into the pillar-shaped semiconductor layer 12 from a silicide layer 18, which is a layer formed to surround a middle portion of the pillar-shaped semiconductor layer 12 and contains the donor impurity. Gate oxide layers 19a to 19d are formed on a side surface of the pillar-shaped semiconductor layer 12. Etching is performed with a single mask to form first to fourth gate conductor layers 21aa, 22aa, 22ba, and 21ba and a silicide layer 18a, which have the same shape as viewed in plan view. An N+ layer 23 is formed on a top portion of the pillar-shaped semiconductor layer 12.