公开(公告)号：US20240356548A1

公开(公告)日：2024-10-24

申请号：US18763451

申请日：2024-07-03

申请人： Altera Corporation

发明人： Pai Ho Bong ,  Sean Woei Voon ,  Shyue Loong Lim ,  Chong Xin Tan

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315 ,  H03K19/018528 ,  H03K19/018585

摘要： An integrated circuit includes an output driver circuit having first and second transistors coupled to an external pad of the integrated circuit and first and second multiplexer circuits. The first multiplexer circuit is configurable to cause the first transistor to be controlled by a first voltage during a data output mode of operation and to couple a first control input of the first transistor to the external pad during a hot-socket protection mode of operation. The second multiplexer circuit is configurable to cause the second transistor to be controlled by a second voltage during the data output mode of operation and to couple a second control input of the second transistor to the external pad during the hot-socket protection mode of operation.

公开(公告)号：US20240321716A1

公开(公告)日：2024-09-26

申请号：US18680058

申请日：2024-05-31

申请人： Altera Corporation

发明人： Md Altaf Hossain ,  Atul Maheshwari ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

IPC分类号： H01L23/498 ,  G06F30/31 ,  G06F115/10

CPC分类号： H01L23/49838 ,  G06F30/31 ,  G06F2115/10

摘要： An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.

公开(公告)号：US20240241994A1

公开(公告)日：2024-07-18

申请号：US18620757

申请日：2024-03-28

申请人： Altera Corporation

发明人： Michael Neve de Mevergnies

IPC分类号： G06F21/86 ,  G06F21/60 ,  G06F21/79

CPC分类号： G06F21/86 ,  G06F21/602 ,  G06F21/79 ,  G06F2221/2143

摘要： Anti-tamper systems and methods for protecting integrated circuit devices are provided. An integrated circuit device making use of an anti-tamper system may include memory and a device manager. The memory may store a count of resets of the integrated circuit device having a duration less than a threshold reset duration. The device manager may perform an anti-tamper operation when the count of resets exceeds a threshold number of resets.

公开(公告)号：US12026008B2

公开(公告)日：2024-07-02

申请号：US17973428

申请日：2022-10-25

申请人： Intel Corporation

发明人： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

IPC分类号： G06F1/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC分类号： G06F1/10 ,  H01L23/3114 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/14515 ,  H01L2924/00012

摘要： An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

公开(公告)号：US20240193331A1

公开(公告)日：2024-06-13

申请号：US18584339

申请日：2024-02-22

申请人： Altera Corporation

发明人： Michael Kinsner ,  Byron Sinclair ,  Gregory Nash

IPC分类号： G06F30/33

CPC分类号： G06F30/33

摘要： An integrated circuit includes configurable logic circuit blocks that are configurable with a first configuration bitstream according to a coarse grained configuration. The coarse grained configuration implements an aggregate circuit structure of the configurable logic circuit blocks. The configurable logic circuit blocks are configurable with a second configuration bitstream according to a fine grained configuration. A total number of the first and the second configuration bits is fewer than a single fine grained configuration bitstream.

公开(公告)号：US20240192983A1

公开(公告)日：2024-06-13

申请号：US18412098

申请日：2024-01-12

申请人： Altera Corporation

发明人： Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis ,  Jiefan Zhang

IPC分类号： G06F9/455 ,  G06F13/28 ,  G06F13/40

CPC分类号： G06F9/45558 ,  G06F13/28 ,  G06F13/4022 ,  G06F2009/45595 ,  G06F2213/0038 ,  G06F2213/28

摘要： A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

公开(公告)号：US12007929B2

公开(公告)日：2024-06-11

申请号：US17067365

申请日：2020-10-09

申请人： Intel Corporation

发明人： Anshuman Thakur ,  Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Mahesh Kumashikar

IPC分类号： G06F13/40

CPC分类号： G06F13/4068

摘要： A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

公开(公告)号：US20240113985A1

公开(公告)日：2024-04-04

申请号：US18538386

申请日：2023-12-13

申请人： Altera Corporation

发明人： Kenneth Taylor ,  Robert Critchlow

IPC分类号： H04L47/52 ,  H04L47/12 ,  H04L47/6295

CPC分类号： H04L47/527 ,  H04L47/12 ,  H04L47/6295

摘要： An integrated circuit includes queue circuits for storing packets, a scheduler circuit that schedules the packets received from the queue circuits to be provided in an output, and a traffic manager circuit that disables one of the queue circuits from transmitting any of the packets to the scheduler circuit based at least in part on a bandwidth in the output scheduled for a subset of the packets received from the one of the queue circuits.

公开(公告)号：US20240113014A1

公开(公告)日：2024-04-04

申请号：US18539193

申请日：2023-12-13

申请人： Altera Corporation

发明人： Krishna Bharath Kolluru ,  Atul Maheshwari ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Jeffrey Chromczak

IPC分类号： H01L23/525 ,  H01L23/528 ,  H01L27/105

CPC分类号： H01L23/525 ,  H01L23/528 ,  H01L27/105

摘要： An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.

公开(公告)号：US20240078211A1

公开(公告)日：2024-03-07

申请号：US18368492

申请日：2023-09-14

申请人： Altera Corporation

发明人： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC分类号： G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/12 ,  G06F13/28 ,  G06F17/14

CPC分类号： G06F15/7825 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/541 ,  G06F13/124 ,  G06F13/28 ,  G06F17/142

摘要： An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.