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    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME 有权
    半导体存储器件及其接收方法

    公开(公告)号：US20140362652A1

    公开(公告)日：2014-12-11

    申请号：US14355120

    申请日：2012-03-22

    申请人： Zhijiong Luo ,  Zhengyong Zhu ,  Haizhou Yin ,  Huilong Zhu

    发明人： Zhijiong Luo ,  Zhengyong Zhu ,  Haizhou Yin ,  Huilong Zhu

    IPC分类号： H01L27/105 ,  H01L29/267 ,  G11C7/00 ,  H01L29/786

    CPC分类号： H01L27/1052 ,  G11C5/06 ,  G11C7/00 ,  G11C8/16 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  H01L29/267 ,  H01L29/7869

    摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

    摘要翻译： 公开了一种半导体存储器件及其访问方法。 半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和 第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合 到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。 半导体存储器件增加了集成度并降低了刷新频率。

    Semiconductor memory device and method for accessing the same
    2.
    发明授权
    Semiconductor memory device and method for accessing the same 有权
    半导体存储器件及其访问方法

    公开(公告)号：US09542990B2

    公开(公告)日：2017-01-10

    申请号：US13508204

    申请日：2012-02-28

    申请人： Zhengyong Zhu ,  Zhijiong Luo

    发明人： Zhengyong Zhu ,  Zhijiong Luo

    IPC分类号： G11C13/02 ,  G11C11/403 ,  G11C13/00 ,  H01L27/108

    CPC分类号： G11C11/403 ,  G11C13/0007 ,  H01L27/108

    摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.

    摘要翻译： 公开了一种半导体存储器件及其访问方法。 半导体存储器件包括氧化物异质结晶体管，其包括：氧化物衬底; 氧化物基板上的氧化膜，其中氧化物基板和氧化膜之间的界面层表现为二维电子气; 源电极和漏电极位于氧化膜上并与界面层电连接; 氧化膜上的前门; 以及在所述氧化物基板的下表面上的背栅极，其中所述氧化物异质结晶体管的源电极和漏电极分别与用于读取操作的第一字线和第一位线连接，并且其中所述前栅极和 后门分别与用于写入操作的第二字线和第二位线连接。

    Semiconductor memory device and method for accessing the same
    3.
    发明授权
    Semiconductor memory device and method for accessing the same 有权
    半导体存储器件及其访问方法

    公开(公告)号：US09236384B2

    公开(公告)日：2016-01-12

    申请号：US14355120

    申请日：2012-03-22

    申请人： Zhijiong Luo ,  Zhengyong Zhu ,  Haizhou Yin ,  Huilong Zhu

    发明人： Zhijiong Luo ,  Zhengyong Zhu ,  Haizhou Yin ,  Huilong Zhu

    IPC分类号： G11C11/405 ,  G11C5/06 ,  G11C5/02 ,  G11C7/00 ,  H01L27/105 ,  G11C11/404 ,  H01L29/267 ,  H01L29/786 ,  G11C8/16 ,  H01L27/108

    CPC分类号： H01L27/1052 ,  G11C5/06 ,  G11C7/00 ,  G11C8/16 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  H01L29/267 ,  H01L29/7869

    摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

    摘要翻译： 公开了一种半导体存储器件及其访问方法。 半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和 第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合 到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。 半导体存储器件增加了集成度并降低了刷新频率。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME 有权
    半导体存储器件及其接收方法

    公开(公告)号：US20130208551A1

    公开(公告)日：2013-08-15

    申请号：US13508204

    申请日：2012-02-28

    申请人： Zhengyong Zhu ,  Zhijiong Luo

    发明人： Zhengyong Zhu ,  Zhijiong Luo

    IPC分类号： G11C7/00 ,  H01L29/20

    CPC分类号： G11C11/403 ,  G11C13/0007 ,  H01L27/108

    摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.

    摘要翻译： 公开了一种半导体存储器件及其访问方法。 半导体存储器件包括氧化物异质结晶体管，其包括：氧化物衬底; 氧化物基板上的氧化膜，其中氧化物基板和氧化膜之间的界面层表现为二维电子气; 源电极和漏电极位于氧化膜上并与界面层电连接; 氧化膜上的前门; 以及在所述氧化物基板的下表面上的背栅极，其中所述氧化物异质结晶体管的源电极和漏电极分别与用于读取操作的第一字线和第一位线连接，并且其中所述前栅极和 后门分别与用于写入操作的第二字线和第二位线连接。

    Efficient transistor-level circuit simulation
    5.
    发明授权
    Efficient transistor-level circuit simulation 失效
    高效的晶体管级电路仿真

    公开(公告)号：US07555416B2

    公开(公告)日：2009-06-30

    申请号：US11777211

    申请日：2007-07-12

    申请人： Chung-Kuan Cheng ,  Zhengyong Zhu

    发明人： Chung-Kuan Cheng ,  Zhengyong Zhu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.

    摘要翻译： 描述了基于两阶段牛顿 - 拉夫逊方法来执行诸如晶体管之类的非线性电路部件的电路分析的技术。