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    High speed clock distribution transmission line network
    3.
    发明授权
    High speed clock distribution transmission line network 有权
    高速时钟分配传输线网络

    公开(公告)号：US07679416B2

    公开(公告)日：2010-03-16

    申请号：US11596968

    申请日：2005-05-23

    申请人： Chung-Kuan Cheng ,  Hongyu Chen

    发明人： Chung-Kuan Cheng ,  Hongyu Chen

    IPC分类号： H03K19/003

    CPC分类号： G06F1/10 ,  H03K5/15013

    摘要： The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform, is used to control clock skew, even at frequencies extending into the gigahertz range. In an exemplary embodiment of the invention, an overlay includes differential pairs of transmission lines that connect the drivers of a clock distribution tree. In preferred embodiments of the invention, an H-tree clock distribution scheme is overlayed with a spiral of transmission lines, each realized by a differential conductors and driven using a sinusoidal standing wave to distribute global clock signals into local regions of the chip. Each transmission line connects drivers in the H-tree that are at the same level of the H-tree. In a VLSI chip according to an embodiment of the invention, the transmission line overlay delivers sinusoidal clock signals to local areas that are locally converted into digital clock signals. The invention thus presents a passive technique for clock distribution.

    摘要翻译： 本发明涉及一种用于时钟分配的方法，并且VLSI电路包括时钟分配网络。 在本发明的方法中，传输线被图案化以便连接时钟树和周期性波形时钟，优选正弦波形，用于控制时钟偏移，即使在延伸到千兆赫兹范围内的频率。 在本发明的示例性实施例中，覆盖层包括连接时钟分配树的驱动器的差分传输线对。 在本发明的优选实施例中，H树时钟分配方案用传输线的螺旋线叠加，每个传输线由差分导体实现，并使用正弦驻波来驱动，以将全局时钟信号分配到芯片的局部区域。 每个传输线连接H树中与H-tree相同级别的驱动程序。 在根据本发明的实施例的VLSI芯片中，传输线覆盖层将正弦时钟信号递送到局部转换成数字时钟信号的局部区域。 因此，本发明提出了一种用于时钟分配的无源技术。

    High Speed Clock Distribution Transmission Line Network
    9.
    发明申请
    High Speed Clock Distribution Transmission Line Network 有权
    高速时钟分配传输线网络

    公开(公告)号：US20080030252A1

    公开(公告)日：2008-02-07

    申请号：US11596968

    申请日：2005-05-23

    申请人： Chung-Kuan Cheng ,  Hongyu Chen

    发明人： Chung-Kuan Cheng ,  Hongyu Chen

    IPC分类号： H03K19/003

    CPC分类号： G06F1/10 ,  H03K5/15013

    摘要： The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform, is used to control clock skew, even at frequencies extending into the gigahertz range. In an exemplary embodiment of the invention, an overlay includes differential pairs of transmission lines that connect the drivers of a clock distribution tree. In preferred embodiments of the invention, an H-tree clock distribution scheme is overlayed with a spiral of transmission lines, each realized by a differential conductors and driven using a sinusoidal standing wave to distribute global clock signals into local regions of the chip. Each transmission line connects drivers in the H-tree that are at the same level of the H-tree. In a VLSI chip according to an embodiment of the invention, the transmission line overlay delivers sinusoidal clock signals to local areas that are locally converted into digital clock signals. The invention thus presents a passive technique for clock distribution.

    摘要翻译： 本发明涉及一种用于时钟分配的方法，并且VLSI电路包括时钟分配网络。 在本发明的方法中，传输线被图案化以便连接时钟树和周期性波形时钟，优选正弦波形，用于控制时钟偏移，即使在延伸到千兆赫兹范围内的频率。 在本发明的示例性实施例中，覆盖层包括连接时钟分配树的驱动器的差分传输线对。 在本发明的优选实施例中，H树时钟分配方案用传输线的螺旋线叠加，每个传输线由差分导体实现，并使用正弦驻波来驱动，以将全局时钟信号分配到芯片的局部区域。 每个传输线连接H树中与H-tree相同级别的驱动程序。 在根据本发明的实施例的VLSI芯片中，传输线覆盖层将正弦时钟信号递送到局部转换成数字时钟信号的局部区域。 因此，本发明提出了一种用于时钟分配的无源技术。