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    Semiconductor device
    2.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20070029641A1

    公开(公告)日：2007-02-08

    申请号：US11498188

    申请日：2006-08-03

    申请人： Tsuyoshi Hamatani ,  Yukitoshi Ota

    发明人： Tsuyoshi Hamatani ,  Yukitoshi Ota

    IPC分类号： H01L23/544

    CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.

    摘要翻译： 沿着半导体元件区域和划线格栅区域之间的边界连续地形成密封环，辅助部件沿着密封环间歇地布置，密封环由金属层构成。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07777304B2

    公开(公告)日：2010-08-17

    申请号：US11498188

    申请日：2006-08-03

    申请人： Tsuyoshi Hamatani ,  Yukitoshi Ota

    发明人： Tsuyoshi Hamatani ,  Yukitoshi Ota

    IPC分类号： H01L23/544

    CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.

    摘要翻译： 沿着半导体元件区域和划线格栅区域之间的边界连续地形成密封环，辅助部件沿着密封环间歇地布置，密封环由金属层构成。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08710667B2

    公开(公告)日：2014-04-29

    申请号：US13289683

    申请日：2011-11-04

    申请人： Hiroshige Hirano ,  Yukitoshi Ota

    发明人： Hiroshige Hirano ,  Yukitoshi Ota

    IPC分类号： H01L23/48

    CPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.

    摘要翻译： 半导体器件包括设置在第一互连层上方或下方的第一互连层和第二互连层。 第一互连层包括多个第一互连块，并且在每个第一互连块中，第一互连具有第一电位，并且在至少两个或更多个方向上延伸，并且第二互连具有第二电位，并且延伸 在至少两个或更多个方向。 第二互连层包括第三互连，其将一对相邻的第一互连块中的一个的第一互连与该对相邻的第一互连块中的另一个的第一互连电连接，以及将第二互连电连接的第四互连 所述一对相邻的第一互连块中的一个和所述一对相邻的第一互连块中的另一个的所述第二互连。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08421236B2

    公开(公告)日：2013-04-16

    申请号：US12976618

    申请日：2010-12-22

    申请人： Yukitoshi Ota ,  Hiroshige Hirano ,  Yutaka Itou

    发明人： Yukitoshi Ota ,  Hiroshige Hirano ,  Yutaka Itou

    IPC分类号： H01L23/48

    CPC分类号： H01L24/05 ,  H01L23/522 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082

    摘要： A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.

    摘要翻译： 半导体器件包括形成在半导体衬底上的电极焊盘，并且是用于外部电连接的连接部分; 多层体，包括形成在所述半导体衬底和所述连接部之间的多个绝缘膜中的多个第一互连层，并且包括连接到所述连接部的上互连件，以及通孔，被配置为连接所述第一互连层; 形成在所述多个绝缘膜中的环体，以在不插入空间的情况下包围所述多层体，并且包括多个第二互连层和至少一条经由线连接所述第二互连层的线; 以及将连接部电连接到内部电路的引线。 多层体通过多个第一互连层中的至少一个连接到环体。 引线与环体连接。