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    Semiconductor memory device including standby mode for reducing current consumption of delay locked loop
    1.
    发明授权
    Semiconductor memory device including standby mode for reducing current consumption of delay locked loop 有权
    半导体存储器件包括用于减少延迟锁定环路的电流消耗的待机模式

    公开(公告)号：US06678206B2

    公开(公告)日：2004-01-13

    申请号：US10106931

    申请日：2002-03-25

    Applicant: Yong-Gyu Chu ,  Kyu-Chan Lee

    Inventor： Yong-Gyu Chu ,  Kyu-Chan Lee

    IPC: G11C800

    CPC classification number: G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/0891

    Abstract: A semiconductor memory device including a delay locked loop (DLL) that is capable of turning off the DLL in a precharge mode while maintaining locking information stored before the DLL operates in the precharge mode is provided. The DLL includes an ON/OFF mode for turning the DLL on or off. The DLL also includes a standby mode for turning the DLL off while still maintaining locking information stored before the DLL operates in a precharge mode in response to the activation of a standby enabling signal. The standby enabling signal is inactive when the DLL locks. The standby enabling signal is active when DLL lock is complete.

    Abstract translation: 提供一种包括延迟锁定环（DLL）的半导体存储器件，其能够在保持DLL在预充电模式之前存储的锁定信息的同时以预充电模式关闭DLL。 该DLL包括用于打开或关闭DLL的ON / OFF模式。 DLL还包括用于响应于待机使能信号的激活而在DLL在预充电模式之前存储的锁定信息的同时仍然保持关闭DLL的待机模式。 当DLL锁定时，待机启用信号无效。 当DLL锁定完成时，待机启用信号有效。

    Semiconductor memory device with stress circuit and method for supplying a stress voltage thereof
    3.
    发明授权
    Semiconductor memory device with stress circuit and method for supplying a stress voltage thereof 失效
    具有应力电路的半导体存储器件及其应力电压的提供方法

    公开(公告)号：US5657282A

    公开(公告)日：1997-08-12

    申请号：US400995

    申请日：1995-03-09

    Applicant: Kyu-Chan Lee

    Inventor： Kyu-Chan Lee

    IPC: G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  G11C29/56

    CPC classification number: G11C29/50 ,  G11C11/401

    Abstract: A semiconductor integrated circuit with a stress circuit and a stress voltage supplying method thereof ensures the reliability of the device. The semiconductor integrated circuit has a stress enable circuit for generating an enable signal during a test operation of the chip and for enabling the test operation, a stress voltage supplying circuit for supplying a first stress voltage and a second stress voltage in response to an output signal of the stress enable circuit during the test operation, and a sensing delay control circuit for receiving the first and second stress voltages and for delaying an operation of the sense amp control circuit during the test operation. During the test operation, the first and second stress voltages are supplied to word lines adjacent to each other in response to the output signal of the stress enable circuit, and a state of a selected memory cell by the word line is sensed in response to an output signal of the sensing delay control circuit.

    Abstract translation: 具有应力电路和应力电压提供方法的半导体集成电路确保了器件的可靠性。 半导体集成电路具有应力使能电路，用于在芯片的测试操作期间产生使能信号并使能测试操作;应力电压供应电路，用于响应输出信号提供第一应力电压和第二应力电压 以及用于接收第一和第二应力电压并用于在测试操作期间延迟读出放大器控制电路的操作的感测延迟控制电路。 在测试操作期间，第一和第二应力电压响应于应力使能电路的输出信号被提供给彼此相邻的字线，并且响应于一个字线检测所选择的存储单元的状态 感测延迟控制电路的输出信号。

    Layout structure of bit line sense amplifiers for a semiconductor memory device
    5.
    发明授权
    Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
    用于半导体存储器件的位线读出放大器的布局结构

    公开(公告)号：US08310853B2

    公开(公告)日：2012-11-13

    申请号：US12987539

    申请日：2011-01-10

    Applicant: Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    Inventor： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC: G11C5/02

    CPC classification number: G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    Abstract translation: 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    METHOD OF OUTPUTTING TEMPERATURE DATA IN SEMICONDUCTOR DEVICE AND TEMPERATURE DATA OUTPUT CIRCUIT THEREFOR
    6.
    发明申请
    METHOD OF OUTPUTTING TEMPERATURE DATA IN SEMICONDUCTOR DEVICE AND TEMPERATURE DATA OUTPUT CIRCUIT THEREFOR 有权
    在半导体器件中输出温度数据的方法及其温度数据输出电路

    公开(公告)号：US20100109753A1

    公开(公告)日：2010-05-06

    申请号：US12605032

    申请日：2009-10-23

    Applicant: YUN-YOUNG LEE ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    Inventor： YUN-YOUNG LEE ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    IPC: H01L37/00

    CPC classification number: G01K7/015 ,  G01K2219/00

    Abstract: A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

    Abstract translation: 提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。 响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。 通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。 响应于比较信号来改变温度数据。 因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

    Reset signal generator in semiconductor device
    8.
    发明申请
    Reset signal generator in semiconductor device 有权
    半导体器件中的复位信号发生器

    公开(公告)号：US20070152721A1

    公开(公告)日：2007-07-05

    申请号：US11511850

    申请日：2006-08-29

    Applicant: Myung-Gyoo Won ,  Kyu-Chan Lee

    Inventor： Myung-Gyoo Won ,  Kyu-Chan Lee

    IPC: H03L7/00

    CPC classification number: H03K17/223 ,  G11C5/147 ,  H03K17/145

    Abstract: A reset signal generator includes an output unit, a trip signal generator, an inverter unit, and a variation reducing unit. The output unit generates a reset signal from a pre-reset signal, and the reset signal follows a supply voltage signal before transitioning to a ground level when the supply voltage signal reaches a tripping voltage. The variation reducing unit is coupled to the inverter unit for reducing a range of the tripping voltage with temperature variations.

    Abstract translation: 复位信号发生器包括输出单元，跳闸信号发生器，逆变器单元和变化减少单元。 输出单元从预复位信号产生复位信号，并且当电源电压信号达到跳闸电压时，复位信号在转换到接地电平之前跟随电源电压信号。 变化减小单元耦合到逆变器单元，用于随着温度变化减小跳闸电压的范围。

    Reference voltage generator with fast start-up and low stand-by power
    9.
    发明授权
    Reference voltage generator with fast start-up and low stand-by power 失效
    参考电压发生器具有快速启动和低待机功率

    公开(公告)号：US5703475A

    公开(公告)日：1997-12-30

    申请号：US671145

    申请日：1996-06-24

    Applicant: Kyu-Chan Lee ,  Jai-Hoon Sim

    Inventor： Kyu-Chan Lee ,  Jai-Hoon Sim

    IPC: G11C11/413 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G05F3/16

    CPC classification number: G05F3/242

    Abstract: A reference voltage generator includes a pull-up stage which pulls a reference voltage signal rapidly up toward 1/2Vcc at power-up. The pull-up stage is controlled by a controller which has a comparator and control voltage generator which are disabled after the pull-up operation is terminated so as to reduce stand-by current consumption. The controller includes a pair of NAND gates cross connected as an RS flip-flop to turn on the pull-up stage at power up. A boost signal allows the flip-flop to enable the comparator and control voltage generator after the power supply has stabilized. When the reference voltage signal reaches 1/2Vcc, the comparator sets the flip flop which turns off the pull-up stage and disables the comparator and control voltage generator.

    Abstract translation: 一个参考电压发生器包括一个上拉电平，它在上电时将参考电压信号快速上升至+ E，加1/2 + EE Vcc。 上拉级由控制器控制，控制器具有比较器和控制电压发生器，在上拉操作结束后禁止，以减少待机电流消耗。 控制器包括一对NAND门，它们作为RS触发器交叉连接，以在上电时接通上拉电平。 升压信号允许触发器在电源稳定后使能比较器和控制电压发生器。 当参考电压信号达到+ E，fra 1/2 + EE Vcc时，比较器设置关闭上拉电平的触发器，并禁止比较器和控制电压发生器。

    Method of outputting temperature data in semiconductor device and temperature data output circuit therefor
    10.
    发明授权
    Method of outputting temperature data in semiconductor device and temperature data output circuit therefor 有权
    在半导体器件中输出温度数据的方法及其温度数据输出电路

    公开(公告)号：US08322922B2

    公开(公告)日：2012-12-04

    申请号：US12605032

    申请日：2009-10-23

    Applicant: Yun-Young Lee ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    Inventor： Yun-Young Lee ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    IPC: G01K7/01 ,  G01K7/14

    CPC classification number: G01K7/015 ,  G01K2219/00

    Abstract: A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

    Abstract translation: 提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。 响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。 通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。 响应于比较信号来改变温度数据。 因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

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