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    Reference buffer circuits for providing reference voltages
    1.
    发明授权
    Reference buffer circuits for providing reference voltages 有权
    用于提供参考电压的参考缓冲电路

    公开(公告)号：US07956597B2

    公开(公告)日：2011-06-07

    申请号：US12145298

    申请日：2008-06-24

    申请人： Ying-Min Liao ,  Yu-Hsin Lin

    发明人： Ying-Min Liao ,  Yu-Hsin Lin

    IPC分类号： G05F3/16

    CPC分类号： G05F1/56

    摘要： A reference buffer circuit provides a reference voltage at an output node and comprises a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising a third MOS transistor. A positive input terminal of the amplifier receives an input voltage. A gate of the first MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to a negative input terminal of the amplifier. A gate of the second MOS transistor is coupled to the drain of the first MOS transistor, a source is coupled to a first voltage source, and a drain is coupled to the source of the first MOS transistor. A gate of the third MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to the output node.

    摘要翻译： 参考缓冲电路在输出节点处提供参考电压，并且包括包括放大器和第一和第二MOS晶体管的闭环分支以及包括第三MOS晶体管的开环分支。 放大器的正输入端接收输入电压。 第一MOS晶体管的栅极耦合到放大器的输出端，源极耦合到放大器的负输入端。 第二MOS晶体管的栅极耦合到第一MOS晶体管的漏极，源极耦合到第一电压源，漏极耦合到第一MOS晶体管的源极。 第三MOS晶体管的栅极耦合到放大器的输出端，源耦合到输出节点。

    Operational amplifier circuits
    3.
    发明授权
    Operational amplifier circuits 有权
    运算放大器电路

    公开(公告)号：US08890611B2

    公开(公告)日：2014-11-18

    申请号：US13612784

    申请日：2012-09-12

    申请人： Hung-Chieh Tsai ,  Chi-Lun Lo ,  Chen-Yen Ho ,  Yu-Hsin Lin

    发明人： Hung-Chieh Tsai ,  Chi-Lun Lo ,  Chen-Yen Ho ,  Yu-Hsin Lin

    IPC分类号： H03F3/45 ,  H03F3/193 ,  H03F1/14 ,  H03F1/32 ,  H03F3/30

    CPC分类号： H03F3/45179 ,  H03F1/14 ,  H03F1/3211 ,  H03F1/483 ,  H03F3/193 ,  H03F3/3023 ,  H03F3/45 ,  H03F3/45076 ,  H03F3/45188 ,  H03F2200/36 ,  H03F2203/45222 ,  H03F2203/45521 ,  H03F2203/45526 ,  H03F2203/45626

    摘要： An operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.

    摘要翻译： 运算放大器电路包括第一级放大器电路，第二级放大器电路和第一前馈电路。 第一级放大器电路耦合到第一输入节点，用于接收第一输入信号并放大第一输入信号以产生第一放大信号。 第二级放大器电路耦合到第一级放大器电路，用于接收第一放大信号并放大第一放大信号以在第一输出节点产生第一输出信号。 第一前馈电路耦合在第一输入节点和第二级放大器电路之间，用于将第一输入信号向前馈送到第二级放大器电路。

    Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method
    6.
    发明授权
    Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method 有权
    具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法

    公开(公告)号：US08344921B2

    公开(公告)日：2013-01-01

    申请号：US13072797

    申请日：2011-03-28

    申请人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

    发明人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

    IPC分类号： H03M3/00

    CPC分类号： H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

    摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.

    摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

    Method for fabricating a surface acoustic wave device
    7.
    发明授权
    Method for fabricating a surface acoustic wave device 有权
    声表面波装置的制造方法

    公开(公告)号：US08028389B2

    公开(公告)日：2011-10-04

    申请号：US11944207

    申请日：2007-11-21

    申请人： Jyh-Shin Chen ,  Sheng-Wen Chen ,  Hui-Ling Kao ,  Yu-Sheng Kung ,  Yu-Hsin Lin ,  Yi-Chiuen Hu

    发明人： Jyh-Shin Chen ,  Sheng-Wen Chen ,  Hui-Ling Kao ,  Yu-Sheng Kung ,  Yu-Hsin Lin ,  Yi-Chiuen Hu

    IPC分类号： H04R17/10 ,  B44C1/22

    CPC分类号： H03H9/02622 ,  H03H3/08 ,  Y10T29/42 ,  Y10T29/49155

    摘要： A novel surface acoustic wave device with a decreased velocity dispersion and a low insertion loss as well as the fabrication method therefore is provided. The surface acoustic wave device includes a substrate, an insulating layer with an indentation on the substrate, a silicon layer divided by an etched window with a first portion on the insulating layer and a second portion suspended above the indentation, a piezoelectric layer on the first and the second portions of the silicon layer, and at least an electrode on the piezoelectric layer.

    摘要翻译： 提供了一种具有降低的速度色散和低插入损耗的新型弹性表面波器件及其制造方法。 表面声波装置包括基板，在基板上具有凹陷的绝缘层，由蚀刻窗口分隔的硅层，绝缘层上具有第一部分，第二部分悬置在凹陷部分上，第一部分上的压电层 和硅层的第二部分，以及压电层上的至少一个电极。

    TRACK AND HOLD CIRCUIT AND RELATED RECEIVING DEVICE WITH TRACK AND HOLD CIRCUIT EMPLOYED THEREIN
    8.
    发明申请
    TRACK AND HOLD CIRCUIT AND RELATED RECEIVING DEVICE WITH TRACK AND HOLD CIRCUIT EMPLOYED THEREIN 有权
    跟踪和保持电路跟踪和相关接收设备跟踪并保持已使用的电路

    公开(公告)号：US20110181334A1

    公开(公告)日：2011-07-28

    申请号：US12695164

    申请日：2010-01-28

    申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Chi-Lun Lo ,  Jong-Woei Chen

    发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Chi-Lun Lo ,  Jong-Woei Chen

    IPC分类号： H03L5/00

    CPC分类号： H03G3/3052 ,  H03G1/0088

    摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.

    摘要翻译： 运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到 运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。