公开(公告)号：US07608488B2

公开(公告)日：2009-10-27

申请号：US11874481

申请日：2007-10-18

Applicant: Yasuyuki Baba ,  Susumu Yoshikawa

Inventor： Yasuyuki Baba ,  Susumu Yoshikawa

IPC: H01L21/82

CPC classification number: H01L29/42336 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7881

Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.

Abstract translation: 一种用于制造第一半导体器件的半导体存储器件的制造方法和其中电池阵列比小于第一半导体器件的半导体器件的制造方法，所述制造方法形成第一元件隔离绝缘膜的高度 所述第一半导体器件的存储单元阵列区域为预定高度，通过使用具有用于暴露所述第一存储单元阵列区域的整体的第一开口的第一蚀刻掩模在预定条件下进行蚀刻处理，并且形成 第二存储单元阵列区域的第二元件隔离绝缘膜和所述第二半导体器件的外围电路区域的一部分以预定高度，通过使用具有用于曝光的第二开口的第二蚀刻掩模在所述预定条件下进行蚀刻处理 所述第二存储单元阵列区域的整体a d用于暴露所述外围电路区域的一部分的第三开口。

公开(公告)号：US20080258201A1

公开(公告)日：2008-10-23

申请号：US11874481

申请日：2007-10-18

Applicant: Yasuyuki BABA ,  Susumu Yoshikawa

Inventor： Yasuyuki BABA ,  Susumu Yoshikawa

IPC: H01L29/788 ,  H01L21/3065

CPC classification number: H01L29/42336 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7881

Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.

Abstract translation: 一种用于制造第一半导体器件的半导体存储器件的制造方法和其中电池阵列比小于第一半导体器件的半导体器件的制造方法，所述制造方法形成第一元件隔离绝缘膜的高度 所述第一半导体器件的存储单元阵列区域为预定高度，通过使用具有用于暴露所述第一存储单元阵列区域的整体的第一开口的第一蚀刻掩模在预定条件下进行蚀刻处理， 第二存储单元阵列区域的第二元件隔离绝缘膜和所述第二半导体器件的外围电路区域的一部分以预定高度，通过使用具有用于曝光的第二开口的第二蚀刻掩模在所述预定条件下进行蚀刻处理 所述第二存储单元阵列区域的整体a d用于暴露所述外围电路区域的一部分的第三开口。

公开(公告)号：US20100043859A1

公开(公告)日：2010-02-25

申请号：US11916014

申请日：2006-05-30

Applicant: Junji Aranami ,  Susumu Yoshikawa

Inventor： Junji Aranami ,  Susumu Yoshikawa

IPC: H01L31/042 ,  H01L33/00 ,  H01G4/008 ,  H01G9/04 ,  B32B3/00 ,  B32B5/00 ,  B05D5/12

CPC classification number: H01G9/2036 ,  C25B1/003 ,  H01G9/2059 ,  H01L51/0086 ,  Y02E10/542 ,  Y02P70/521 ,  Y10T428/24612 ,  Y10T428/249921

Abstract: A composite of a base and an array of needle-like crystals formed on a surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 contains a transparent electrode 2 serving as the base and an array 4 of needle-like crystals 3 formed thereon. The needle-like crystals 3 are made of, for example, zinc oxide. The array 4 includes a first region R1 on the transparent electrode 2 side and a second region R2 on the opposite side to the transparent electrode 2 with respect to the first region R1. A proportion of the cross section of the needle-like crystals 3 in a plane parallel to the surface of the transparent electrode 2 is lower in the second region R2 than in the first region R1, and the surface of the transparent electrode 2 is substantially covered with the needle-like crystals 3 in the first region R1.

Abstract translation: 提供了形成在基体的表面上的针状晶体的基极和阵列的复合体，其中可以以令人满意的方式隔离基极侧和相对于阵列的与基底相反的一侧。 复合体10含有作为基材的透明电极2和形成在其上的针状晶体3的阵列4。 针状晶体3例如由氧化锌构成。 阵列4包括透明电极2侧的第一区域R1和与透明电极2相对于第一区域R1相反一侧的第二区域R2。 针状晶体3在与透明电极2的表面平行的平面中的横截面积的比例在第二区域R2中比在第一区域R1中低，并且透明电极2的表面被基本覆盖 第一区域R1中的针状晶体3。

公开(公告)号：US5356830A

公开(公告)日：1994-10-18

申请号：US627922

申请日：1990-12-17

Applicant: Susumu Yoshikawa ,  Shuichi Samata ,  Satoshi Maeda ,  Shizuo Sawada

Inventor： Susumu Yoshikawa ,  Shuichi Samata ,  Satoshi Maeda ,  Shizuo Sawada

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/43

CPC classification number: H01L21/28525 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76879

Abstract: A semiconductor device and its manufacturing method are provided in which an epitaxial silicon layer is formed by a selective epitaxial growth method over a semiconductor substrate and a polysilicon layer is formed by an ordinary deposition method on the epitaxial silicon layer and these layers and are formed over a semiconductor device in a continuous process within the same furnace for a CVD apparatus.

Abstract translation: 提供一种半导体器件及其制造方法，其中在半导体衬底上通过选择性外延生长方法形成外延硅层，并且通过普通沉积方法在外延硅层和这些层上形成多晶硅层 在用于CVD设备的同一炉内的连续工艺中的半导体器件。

公开(公告)号：US5187566A

公开(公告)日：1993-02-16

申请号：US646496

申请日：1991-01-28

Applicant: Susumu Yoshikawa ,  Junpei Kumagai ,  Shizuo Sawada ,  Yasuo Matsumoto

Inventor： Susumu Yoshikawa ,  Junpei Kumagai ,  Shizuo Sawada ,  Yasuo Matsumoto

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10829 ,  H01L27/10835

Abstract: In a semiconductor memory of the invention, the source or drain of a transfer gate MOS transistor is electrically connected to a charge storage first conductive layer through a third conductive layer.

Abstract translation: 在本发明的半导体存储器中，传输门MOS晶体管的源极或漏极通过第三导电层电连接到电荷存储第一导电层。

公开(公告)号：US4320033A

公开(公告)日：1982-03-16

申请号：US201837

申请日：1980-10-29

Applicant: Susumu Yoshikawa

Inventor： Susumu Yoshikawa

IPC: C11D1/72 ,  C11D1/14 ,  C11D1/75 ,  C11D1/83 ,  C11D17/00

CPC classification number: C11D1/75 ,  C11D1/83 ,  C11D17/006

Abstract: A solid detergent composition, suitable for use in personal hygiene, having improved slough loss and wear rate characteristics is presented. This solid detergent compositions contains:(A) 40 to 89.9% by weight of at least one linear alpha-olefin sulfonate having 12 to 28 carbon atoms,(B) 10 to 60% by weight of at least one, tertiary amine oxide having general formulae (I) and (II) ##STR1## wherein R.sup.1 represents an alkyl group having 16 to 24 carbon atoms, R.sup.2 represents an alkyl group having 1 to 11 carbon atoms, R.sup.3 represents an alkyl group having 1 to 3 carbon atoms, R.sup.4 and R.sup.5 independently represent an alkyl group having 12 to 24 carbon atoms and R.sup.6 represents an alkyl group having 1 to 3 carbon atoms, and(C) 0.1 to 20% by weight of water.

Abstract translation: 提出了一种适用于个人卫生的固体洗涤剂组合物，具有改善的脱落和磨损率特性。 该固体洗涤剂组合物包含：（A）40至89.9重量％的至少一种具有12至28个碳原子的直链α-烯烃磺酸盐，（B）10至60重量％的至少一种具有一般性的叔胺氧化物 式（I）和（II）其中R 1表示碳原子数为16〜24的烷基，R 2表示碳原子数1〜11的烷基，R 3表示烷基 具有1至3个碳原子，R 4和R 5独立地表示具有12至24个碳原子的烷基，R 6表示具有1至3个碳原子的烷基，（C）为0.1至20重量％的水。

公开(公告)号：US20070012989A1

公开(公告)日：2007-01-18

申请号：US11342524

申请日：2006-01-31

Applicant: Susumu Yoshikawa

Inventor： Susumu Yoshikawa

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11519

Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.

Abstract translation: 非易失性半导体存储器包括被配置为在列方向上并行延伸的第一和第二有源区域; 元件隔离区域，被配置为电分离第一和第二有源区域; 多个字线，被构造成在行方向上延伸并由相应的主要部分和相应的端部构成; 以及多个存储单元晶体管，被配置为设置在所述多个字线的各个主要部分和所述第二有效区域之间的交叉点上。 每个存储单元晶体管包括构成存储单元阵列的栅绝缘膜，浮栅电极，栅极间绝缘膜和控制栅电极; 短路区域，被配置为使多个字线的端部电短路; 以及沟槽，其被配置为将端部与多个字线的主要部分分开。

公开(公告)号：US07732854B2

公开(公告)日：2010-06-08

申请号：US11984489

申请日：2007-11-19

Applicant: Susumu Yoshikawa

Inventor： Susumu Yoshikawa

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11519

Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.

Abstract translation: 非易失性半导体存储器包括被配置为在列方向上并行延伸的第一和第二有源区域; 元件隔离区域，被配置为电分离第一和第二有源区域; 多个字线，被构造成在行方向上延伸并由相应的主要部分和相应的端部构成; 以及多个存储单元晶体管，被配置为设置在所述多个字线的各个主要部分和所述第二有效区域之间的交叉点上。 每个存储单元晶体管包括构成存储单元阵列的栅绝缘膜，浮栅电极，栅极间绝缘膜和控制栅电极; 短路区域，被配置为使多个字线的端部电短路; 以及沟槽，其被配置为将端部与多个字线的主要部分分开。

公开(公告)号：US07298005B2

公开(公告)日：2007-11-20

申请号：US11342524

申请日：2006-01-31

Applicant: Susumu Yoshikawa

Inventor： Susumu Yoshikawa

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11519

Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.

公开(公告)号：US5013679A

公开(公告)日：1991-05-07

申请号：US403292

申请日：1989-09-05

Applicant: Jumpei Kumagai ,  Susumu Yoshikawa

Inventor： Jumpei Kumagai ,  Susumu Yoshikawa

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10844 ,  H01L27/10829

Abstract: In a cell capacitor of a dynamic random access memory cell according to the present invention, an insulation film is formed on the surface of a fine trench formed in a silicon semiconductor substrate. A contact hole is formed in the insulation film in a region on the side wall of the trench. A polysilicon film is formed on the side wall of the trench in a hollow-cylindrical shape. A silicon layer is epitaxially and selectively grown on the polysilicon film and on the silicon substrate exposed through the contact hole. The polysilicon film and the silicon layer constitute an information storage electrode. At least the silicon layer of the information storage electrode is electrically connected to a source or a drain region of a transfer transistor of the memory cell. A gate insulation film is formed on the surface of the silicon layer. A counter electrode is formed such that the counter electrode is embedded in the trench.

Abstract translation: 在根据本发明的动态随机存取存储单元的单元电容器中，在形成在硅半导体衬底中的细沟槽的表面上形成绝缘膜。 在沟槽的侧壁上的区域中的绝缘膜中形成接触孔。 在中空圆柱形状的沟槽的侧壁上形成多晶硅膜。 硅层被外延选择性地生长在多晶硅膜上并通过接触孔暴露的硅衬底上。 多晶硅膜和硅层构成信息存储电极。 至少信息存储电极的硅层电连接到存储单元的转移晶体管的源极或漏极区域。 在硅层的表面上形成栅极绝缘膜。 形成对电极使得对电极嵌入沟槽中。