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    Semiconductor device having an SOI substrate
    2.
    发明授权
    Semiconductor device having an SOI substrate 失效
    具有SOI衬底的半导体器件

    公开(公告)号：US06252281B1

    公开(公告)日：2001-06-26

    申请号：US08612456

    申请日：1996-03-07

    Applicant: Tadashi Yamamoto ,  Shizuo Sawada

    Inventor： Tadashi Yamamoto ,  Shizuo Sawada

    IPC: H01L2701

    CPC classification number: H01L27/10894 ,  H01L21/76264 ,  H01L21/76281 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/1203

    Abstract: Silicon oxide layers are provided in a substrate. That part of the silicon oxide layer which is located in a memory cell section MC has a thickness. That part of the silicon oxide layer which is located in a peripheral circuit section PC has a thickness, which is less than the thickness. The memory cell section MC has transistors, each having a source region and a drain region which contact the silicon oxide layer. The peripheral circuit section PC has transistors, each having a source region and a drain region which are spaced apart from the silicon oxide layer. The transistors of the peripheral circuit section PC are provided in well regions. A back-gate bias is applied to the transistors of the peripheral circuit section PC through impurity layers.

    Abstract translation: 氧化硅层设置在基板中。 位于存储单元部分MC中的部分氧化硅层具有厚度。 位于外围电路部分PC中的部分氧化硅层的厚度小于厚度。 存储单元部MC具有各自具有与氧化硅层接触的源极区域和漏极区域的晶体管。 外围电路部分PC具有各自具有与氧化硅层间隔开的源极区域和漏极区域的晶体管。 外围电路部分PC的晶体管设置在阱区中。 背栅极偏置通过杂质层施加到外围电路部分PC的晶体管。

    Dynamic random access memory having bit lines buried in semiconductor substrate
    3.
    发明授权
    Dynamic random access memory having bit lines buried in semiconductor substrate 失效
    具有埋在半导体衬底中的位线的动态随机存取存储器

    公开(公告)号：US5410169A

    公开(公告)日：1995-04-25

    申请号：US20444

    申请日：1993-02-22

    Applicant: Tadashi Yamamoto ,  Shizuo Sawada

    Inventor： Tadashi Yamamoto ,  Shizuo Sawada

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: H01L27/10808

    Abstract: There is provided a DRAM memory cell structure. The semiconductor structure includes a semiconductor substrate of a first conductivity type having a main surface, source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate, word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions, capacitors each having one of the source and drain regions as a storage node electrode, and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.

    Abstract translation: 提供了DRAM存储单元结构。 半导体结构包括：第一导电类型的半导体衬底，具有主表面，形成在半导体衬底的主表面区域中的第二导电类型的源极和漏极区域，字线在第一平面方向上延伸并形成在这些部分上 分别位于源极和漏极区之间的半导体衬底，分别具有源极和漏极区之一的电容器作为存储节点电极，以及掩埋在半导体衬底中并分别电连接到源极或漏极区的位线。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5041887A

    公开(公告)日：1991-08-20

    申请号：US522796

    申请日：1990-05-14

    Applicant: Jumpei Kumagai ,  Shizuo Sawada

    Inventor： Jumpei Kumagai ,  Shizuo Sawada

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: H01L27/10829

    Abstract: In one-transistor.one-capacitor type dynamic memory cell, cell capacitor with a reduced junction leakage current comprises a MOS capacitor which is provided between a semiconductor substrate and a charge storage electrode disposed at a side wall of a trench through a first insulating film, and a stacked capacitor which is provided between the charge storage electrode and a capacitor plate electrode formed on a second insulating film covering the entire surface of the charge storage electrode. The equivalent silicon dioxide thickness of the first insulating film is thicker than that of the second insulating film, and the storage capacitance of the cell capacitor is rendered by a sum of the capacitance of the MOS capacitor and the capacitance of the stacked capacitor because these capacitors are electrically connected in parallel with each other.

    Method for fabricating a semiconductor device
    9.
    发明授权
    Method for fabricating a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US4410375A

    公开(公告)日：1983-10-18

    申请号：US307875

    申请日：1981-10-02

    Applicant: Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

    Inventor： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

    IPC: H01L27/10 ,  H01L21/225 ,  H01L21/3105 ,  H01L21/322 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/2255 ,  H01L21/3105 ,  H01L27/10805

    Abstract: A method for fabricating a semiconductor device is disclosed which includes a step of forming contact holes in insulating films on a substrate, forming a silicate glass layer containing an impurity over the entire surface, and performing the phosphorus getter treatment using POCl.sub.3 at a high temperature. Even when the phosphorus getter treatment is performed after the formation of the contact holes, the substrate or electrodes exposed through the contact holes may not be reduced in thickness or damaged. The impurity may be diffused into the substrate from the silicate glass layer through the contact holes.

    Abstract translation: 公开了一种制造半导体器件的方法，其包括在基片上形成绝缘膜中的接触孔的步骤，在整个表面上形成含有杂质的硅酸盐玻璃层，并在高温下使用POCl 3进行磷吸气剂处理。 即使在形成接触孔之后进行磷吸气剂处理，也可能不会使通过接触孔露出的基板或电极的厚度减小或损坏。 杂质可以从硅酸盐玻璃层通过接触孔扩散到衬底中。

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