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    Semiconductor memory device and method of manufacturing the same
    1.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08648467B2

    公开(公告)日：2014-02-11

    申请号：US13458141

    申请日：2012-04-27

    Applicant: Yasuyuki Baba

    Inventor： Yasuyuki Baba

    IPC: H01L23/528 ,  H01L21/44

    CPC classification number: H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.

    Abstract translation: 根据实施例的半导体存储器件的制造方法包括：形成第一堆叠结构; 在所述第一堆叠结构处形成第一条纹部分和第一钩部分; 在所述第一堆叠结构上形成第二堆叠结构; 在第二堆叠结构中形成第二条纹部分和第二钩部分; 重复上述四个步骤一定次数; 以及形成接触所述第一或第二钩部的接触塞。 进行蚀刻以将第一叠层结构的第一堆叠结构除去在比第一堆叠结构高的第二层叠结构中的第二钩部将要形成的区域中的第一层叠结构。 进行蚀刻以在第一层叠结构中的第一层叠结构中的第一层叠结构中将要形成第一钩部的区域中的第二层叠结构移除一层以上。

    Nonvolatile semiconductor memory device
    2.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08228712B2

    公开(公告)日：2012-07-24

    申请号：US12725655

    申请日：2010-03-17

    Applicant: Yasuyuki Baba

    Inventor： Yasuyuki Baba

    IPC: G11C11/00

    CPC classification number: G11C13/0002 ,  G11C2213/71 ,  G11C2213/72

    Abstract: A semiconductor memory device includes a memory cell array configured as an arrangement of memory cells each arranged between a first line and a second line and each including a variable resistor. A control circuit controls a voltage applied to the first line or the second line. A current limiting circuit limits a current flowing through the first line or the second line to a certain upper limit or lower. In a case where a writing operation or an erasing operation to a memory cell is implemented a plural number of times repeatedly, the current limiting circuit sets the upper limit in the writing operation or erasing operation of the p-th time higher than the upper limit in the writing operation or erasing operation of the q-th time (q

    Abstract translation: 半导体存储器件包括存储单元阵列，其被配置为每个布置在第一线路和第二线路之间并且各自包括可变电阻器的存储器单元的布置。 控制电路控制施加到第一线或第二线的电压。 电流限制电路将流过第一线或第二线的电流限制在一定的上限或更低。 在对存储单元的写入操作或擦除操作重复多次的情况下，限流电路将写入操作的上限或第p个时间的擦除操作设置为高于上限 在第q次的写入操作或擦除操作（q

    Gastrostomy Tube Extension Device
    4.
    发明申请
    Gastrostomy Tube Extension Device 有权
    胃造口管扩张装置

    公开(公告)号：US20080208208A1

    公开(公告)日：2008-08-28

    申请号：US11631835

    申请日：2005-04-26

    Applicant: Katsuki Nagata ,  Yasuyuki Baba

    Inventor： Katsuki Nagata ,  Yasuyuki Baba

    IPC: A61M37/00

    CPC classification number: A61J15/0038 ,  A61J15/0015 ,  A61J15/0026 ,  A61J15/0065

    Abstract: To provide a gastrostomy tube extension device which can facilitate insertion or removal of a gastrostomy tube by making the degree of extension of the gastrostomy tube constant. [Means for Resolution] A gastrostomy tube extension device 20 used for inserting and taking out a gastrostomy tube 10 into/from a hole 33 formed on a patient's abdomen, the gastrostomy tube 10 including an outer fixing member 10a to be installed on the skin surface side, an inner fixing member 10c installed on the inner surface side of the stomach wall, and a tube member 10b for connecting the outer fixing member 10a and the inner fixing member 10c, and the gastrostomy tube extension device comprising a rod 21 and an engaging member 22. The rod 21 has a rod-shaped member which can push the center of the distal end of the inner fixing member 10c with its distal portion toward the distal end, and with a plurality of engaging step portions 24a are formed on the proximal portion. The engaging member 22 is also provided with a lower engaging portion 25 which can engage with an outer fixing member 10a and an upper engaging portion 26 which can engage one of the engaging step portions 24a of the rod 21.

    Abstract translation: 提供胃造口管延伸装置，其可以通过使胃造口管的延伸程度恒定来促进胃造口管的插入或移除。 [解决方法]用于将胃造口管10插入/取出形成在患者腹部的孔33中的胃造口管延伸装置20，胃造口管10包括要安装在皮肤上的外固定构件10a 表面侧，安装在胃壁的内表面侧的内固定构件10c和用于连接外固定构件10a和内固定构件10c的管构件10b，以及胃造口管延伸装置，其包括 杆21和接合构件22.杆21具有杆状构件，其可以使其内部固定构件10c的远端的中心的远端部朝向远端推动，并且具有多个接合步骤部分 24 a形成在近端部分上。 接合构件22还设置有可与外部固定构件10a接合的下部接合部25和能够接合杆21的接合台阶部分24a之一的上部接合部26。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20130249113A1

    公开(公告)日：2013-09-26

    申请号：US13599153

    申请日：2012-08-30

    Applicant: Yasuyuki BABA

    Inventor： Yasuyuki BABA

    IPC: H01L23/498

    CPC classification number: H01L23/49844 ,  H01L27/0207 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/141 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions.

    Abstract translation: 半导体存储器件包括沿第一方向延伸的多个第一布线，沿与第一方向交叉的第二方向延伸的多个第二布线，以及包括存储单元的存储单元阵列，存储单元连接到第一布线 第一布线和第二布线的交叉部分中的布线和第二布线。 在存储单元阵列周围的周边区域中形成多个第一虚设布线区域。 接触件形成在周边区域中，接触件沿垂直于第一和第二方向的第三方向延伸。 多个第二虚设布线区域形成在触点的周围。 第二虚拟布线区域的面积的平均值小于第一虚拟布线区域的面积的平均值。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20120299063A1

    公开(公告)日：2012-11-29

    申请号：US13458141

    申请日：2012-04-27

    Applicant: Yasuyuki BABA

    Inventor： Yasuyuki BABA

    IPC: H01L27/04 ,  H01L21/02

    CPC classification number: H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.

    Abstract translation: 根据实施例的半导体存储器件的制造方法包括：形成第一堆叠结构; 在所述第一堆叠结构处形成第一条纹部分和第一钩部分; 在所述第一堆叠结构上形成第二堆叠结构; 在第二堆叠结构中形成第二条纹部分和第二钩部分; 重复上述四个步骤一定次数; 以及形成接触所述第一或第二钩部的接触塞。 进行蚀刻以将第一叠层结构的第一堆叠结构除去在比第一堆叠结构高的第二层叠结构中的第二钩部将要形成的区域中的第一层叠结构。 进行蚀刻以在第一层叠结构中的第一层叠结构中的第一层叠结构中将要形成第一钩部的区域中的第二层叠结构移除一层以上。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20110051493A1

    公开(公告)日：2011-03-03

    申请号：US12725655

    申请日：2010-03-17

    Applicant: Yasuyuki BABA

    Inventor： Yasuyuki BABA

    IPC: G11C11/00 ,  G11C7/00 ,  G11C7/02

    CPC classification number: G11C13/0002 ,  G11C2213/71 ,  G11C2213/72

    Abstract: A semiconductor memory device includes a memory cell array configured as an arrangement of memory cells each arranged between a first line and a second line and each including a variable resistor. A control circuit controls a voltage applied to the first line or the second line. A current limiting circuit limits a current flowing through the first line or the second line to a certain upper limit or lower. In a case where a writing operation or an erasing operation to a memory cell is implemented a plural number of times repeatedly, the current limiting circuit sets the upper limit in the writing operation or erasing operation of the p-th time higher than the upper limit in the writing operation or erasing operation of the q-th time (q

    Abstract translation: 半导体存储器件包括存储单元阵列，其被配置为每个布置在第一线路和第二线路之间并且各自包括可变电阻器的存储器单元的布置。 控制电路控制施加到第一线或第二线的电压。 电流限制电路将流过第一线或第二线的电流限制在一定的上限或更低。 在对存储单元的写入操作或擦除操作重复多次的情况下，限流电路将写入操作的上限或第p个时间的擦除操作设置为高于上限 在第q次的写入操作或擦除操作（q

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20080258201A1

    公开(公告)日：2008-10-23

    申请号：US11874481

    申请日：2007-10-18

    Applicant: Yasuyuki BABA ,  Susumu Yoshikawa

    Inventor： Yasuyuki BABA ,  Susumu Yoshikawa

    IPC: H01L29/788 ,  H01L21/3065

    CPC classification number: H01L29/42336 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7881

    Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.

    Abstract translation: 一种用于制造第一半导体器件的半导体存储器件的制造方法和其中电池阵列比小于第一半导体器件的半导体器件的制造方法，所述制造方法形成第一元件隔离绝缘膜的高度 所述第一半导体器件的存储单元阵列区域为预定高度，通过使用具有用于暴露所述第一存储单元阵列区域的整体的第一开口的第一蚀刻掩模在预定条件下进行蚀刻处理， 第二存储单元阵列区域的第二元件隔离绝缘膜和所述第二半导体器件的外围电路区域的一部分以预定高度，通过使用具有用于曝光的第二开口的第二蚀刻掩模在所述预定条件下进行蚀刻处理 所述第二存储单元阵列区域的整体a d用于暴露所述外围电路区域的一部分的第三开口。

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