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公开(公告)号：US10291192B1
公开(公告)日：2019-05-14
申请号：US15916887
申请日：2018-03-09
Applicant: Xilinx, Inc.
Inventor： Ronan Casey , Chi Fung Poon , Ilias Chlis , Junho Cho
Abstract: Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-gm biasing to provide substantial immunity to process, temperature and voltage variations, for example. Various implementations of series peaking circuit-branch pre-emphasis may advantageously extend overall bandwidth of various circuits (e.g., high-speed track-and-hold circuits).
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公开(公告)号：US11824548B2
公开(公告)日：2023-11-21
申请号：US17555212
申请日：2021-12-17
Applicant: XILINX, INC.
Inventor： Shaojun Ma , Chi Fung Poon
IPC: H03L7/099 , G06F1/06 , H03K17/687
CPC classification number: H03L7/0995 , G06F1/06 , H03K17/6872 , H03K17/6874
Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.
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公开(公告)号：US12160256B2
公开(公告)日：2024-12-03
申请号：US17559592
申请日：2021-12-22
Applicant: XILINX, INC.
Inventor： Chi Fung Poon , Chuen-Huei Chou , Weerachai Neeranartvong , Kevin Zheng
Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.
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公开(公告)号：US11721651B2
公开(公告)日：2023-08-08
申请号：US17037363
申请日：2020-09-29
Applicant: XILINX, INC.
Inventor： Chi Fung Poon , Asma Laraba , Parag Upadhyaya
IPC: H01L23/66 , H01L23/538 , H01L25/16
CPC classification number: H01L23/66 , H01L23/5386 , H01L25/16 , H01L2224/02379
Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.
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Patent Agency Ranking
公开(公告)号：US12126335B2
公开(公告)日：2024-10-22
申请号：US18115588
申请日：2023-02-28
Applicant: XILINX, INC.
Inventor： Li-Yang Chen , Chi Fung Poon , Chuen-Huei Chou
IPC: H04B1/04 , H03K17/00 , H03K17/693 , H04B1/40
CPC classification number: H03K17/693 , H03K17/005 , H04B1/0483 , H04B1/40
Abstract: A transmission system is disclosed including a driver circuit. The driver circuit includes multiplexer circuits that receive parallel data and operate as a differential pair. At least one of the multiplexer circuits is coupled to a first circuit node and a second circuit node of the driver circuit. The at least one the multiplexer circuits outputs serial data from the multiplexer circuits at the first and second circuit nodes. The first and second nodes are coupled to a differential output network. The first and second nodes are coupled to an inductor circuit. The first and second nodes are coupled to a cross-coupled circuit. The inductor circuit drains driver circuit current at the first circuit node. The second circuit node and the cross-coupled circuit steer driver circuit current at the first circuit node and the second circuit node.
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公开(公告)号：US11728962B2
公开(公告)日：2023-08-15
申请号：US17644066
申请日：2021-12-13
Applicant: XILINX, INC.
Inventor： Shaojun Ma , Chi Fung Poon , Kevin Zheng , Parag Upadhyaya
CPC classification number: H04L7/0037 , H03K19/21
Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.
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公开(公告)号：US11003203B2
公开(公告)日：2021-05-11
申请号：US16518365
申请日：2019-07-22
Applicant: Xilinx, Inc.
Inventor： Chi Fung Poon , Asma Laraba , Parag Upadhyaya
Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.
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公开(公告)号：US20200293080A1
公开(公告)日：2020-09-17
申请号：US16518365
申请日：2019-07-22
Applicant: Xilinx, Inc.
Inventor： Chi Fung Poon , Asma Laraba , Parag Upadhyaya
Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.
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公开(公告)号：US09906232B1
公开(公告)日：2018-02-27
申请号：US15455915
申请日：2017-03-10
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Parag Upadhyaya , Chi Fung Poon
CPC classification number: H04L7/0087 , H03M1/007 , H03M1/40 , H03M1/462 , H04B1/0014 , H04L27/0002
Abstract: An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit configured to receive an analog input signal; a digital-to-analog converter (DAC); an adder having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit coupled to an output of the adder and configured to perform a comparison operation; and a control circuit, coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.
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