公开(公告)号：US11133963B1

公开(公告)日：2021-09-28

申请号：US17011595

申请日：2020-09-03

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Ronan Casey

IPC: H04L25/03 ,  H03M1/12 ,  H04B1/12

Abstract: Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.

公开(公告)号：US09876489B1

公开(公告)日：2018-01-23

申请号：US15258696

申请日：2016-09-07

Applicant: Xilinx, Inc.

Inventor： Ronan Casey ,  Catherine Hearne ,  Jinyung Namkoong

IPC: H03K5/05 ,  H03K5/151 ,  H04L7/00 ,  H03K5/06 ,  H03K5/00

CPC classification number: H03K5/05 ,  H03K5/06 ,  H03K5/065 ,  H03K5/135 ,  H03K5/1515 ,  H03K2005/00052 ,  H04L7/0025

Abstract: The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source.

公开(公告)号：US09209809B1

公开(公告)日：2015-12-08

申请号：US14573815

申请日：2014-12-17

Applicant: Xilinx, Inc.

Inventor： Kevin Geary ,  Ronan Casey ,  Declan Carey ,  Thomas Mallard

IPC: H03K19/094 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/018514 ,  H03K19/00384

Abstract: A circuit for controlling output swing in a current-mode logic circuit is described. The circuit comprises a plurality of current-mode logic circuits coupled in series; a first current-mode logic circuit of the plurality of current-mode logic circuits coupled to provide a signal to a second current-mode logic circuit of the plurality of current-mode logic circuits; an amplitude detector coupled to detect an amplitude of the signal received at the second current-mode logic circuit; and a control circuit coupled to the amplitude detector; wherein the control circuit generates an amplitude control signal for a current-mode logic circuit of the plurality of current-mode logic circuits based upon a detected amplitude of the signal received at the second current-mode logic circuit. A method of controlling output swing in a current-mode logic circuit is also disclosed.

Abstract translation: 描述用于控制电流模式逻辑电路中的输出摆幅的电路。 电路包括串联耦合的多个电流模式逻辑电路; 所述多个电流模式逻辑电路中的第一电流模式逻辑电路被耦合以向所述多个电流模式逻辑电路中的第二电流模式逻辑电路提供信号; 振幅检测器，被耦合以检测在第二电流模式逻辑电路处接收的信号的幅度; 以及耦合到所述幅度检测器的控制电路; 其中所述控制电路基于在所述第二电流模式逻辑电路处接收的所述信号的检测幅度，生成所述多个电流模式逻辑电路中的电流模式逻辑电路的幅度控制信号。 还公开了一种控制电流模式逻辑电路中的输出摆幅的方法。

公开(公告)号：US10911060B1

公开(公告)日：2021-02-02

申请号：US16683854

申请日：2019-11-14

Applicant: Xilinx, Inc.

Inventor： Pedro W. Neto ,  Ronan Casey ,  Declan Carey

IPC: H03M1/00 ,  H03M1/46 ,  G11C27/02 ,  H03M1/06 ,  H03M1/16

Abstract: Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi≥1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi≥1, at least one buffer of the Xi buffers may include an integrating buffer, N≥i≥1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.

公开(公告)号：US10291192B1

公开(公告)日：2019-05-14

申请号：US15916887

申请日：2018-03-09

Applicant: Xilinx, Inc.

Inventor： Ronan Casey ,  Chi Fung Poon ,  Ilias Chlis ,  Junho Cho

IPC: H03F3/187 ,  H03F3/45 ,  H03G1/00

Abstract: Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-gm biasing to provide substantial immunity to process, temperature and voltage variations, for example. Various implementations of series peaking circuit-branch pre-emphasis may advantageously extend overall bandwidth of various circuits (e.g., high-speed track-and-hold circuits).