公开(公告)号：US08217470B2

公开(公告)日：2012-07-10

申请号：US12702682

申请日：2010-02-09

申请人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

发明人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651

摘要： A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.

摘要翻译： 场效应结构和用于制造场效应结构的方法包括介于多个源区和漏区之间的含锗通道。 含锗通道与多个源极和漏极区域共面，并且含锗沟道包括锗含量大于多个源极和漏极区的锗含量的含锗材料。

公开(公告)号：US20100200934A1

公开(公告)日：2010-08-12

申请号：US12702682

申请日：2010-02-09

申请人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

发明人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651

摘要： A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.

摘要翻译： 场效应结构和用于制造场效应结构的方法包括介于多个源区和漏区之间的含锗通道。 含锗通道与多个源极和漏极区域共面，并且含锗沟道包括锗含量大于多个源极和漏极区的锗含量的含锗材料。

公开(公告)号：US07842940B2

公开(公告)日：2010-11-30

申请号：US12062164

申请日：2008-04-03

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US07365399B2

公开(公告)日：2008-04-29

申请号：US11333074

申请日：2006-01-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US20080179712A1

公开(公告)日：2008-07-31

申请号：US12062164

申请日：2008-04-03

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US08803243B2

公开(公告)日：2014-08-12

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L21/70

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US08476706B1

公开(公告)日：2013-07-02

申请号：US13343472

申请日：2012-01-04

申请人： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

发明人： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651

摘要： A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

摘要翻译： 通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面， 或硅片的垂直表面。 可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。 普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

公开(公告)号：US20120208337A1

公开(公告)日：2012-08-16

申请号：US13456633

申请日：2012-04-26

申请人： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

发明人： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

摘要翻译： 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US20120168874A1

公开(公告)日：2012-07-05

申请号：US13409693

申请日：2012-03-01

申请人： Sunfei Fang ,  Brian J. Greene ,  Effendi Leobandung ,  Qingqing Liang ,  Edward P. Maciejewski ,  Yanfeng Wang

发明人： Sunfei Fang ,  Brian J. Greene ,  Effendi Leobandung ,  Qingqing Liang ,  Edward P. Maciejewski ,  Yanfeng Wang

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636

摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

摘要翻译： 提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。 含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

公开(公告)号：US08039331B2

公开(公告)日：2011-10-18

申请号：US12120286

申请日：2008-05-14

申请人： Scott D. Allen ,  Cyril Cabral, Jr. ,  Kevin K. Dezfulian ,  Sunfei Fang ,  Brian J. Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement H. Wann ,  Huilong Zhu

发明人： Scott D. Allen ,  Cyril Cabral, Jr. ,  Kevin K. Dezfulian ,  Sunfei Fang ,  Brian J. Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement H. Wann ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/268 ,  H01L21/2686 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/324 ,  H01L29/517 ,  H01L29/665

摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。