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    Semiconductor isolation structures having different configurations in different device regions and method of forming the same
    1.
    发明授权
    Semiconductor isolation structures having different configurations in different device regions and method of forming the same 有权

    公开(公告)号：US11335770B2

    公开(公告)日：2022-05-17

    申请号：US16885286

    申请日：2020-05-28

    Applicant: Winbond Electronics Corp.

    Inventor： Yoshinori Tanaka ,  Wei-Che Chang

    IPC: H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L27/108

    Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

    DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF MANUFACTURING, WRITING AND READING THE SAME
    2.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF MANUFACTURING, WRITING AND READING THE SAME 审中-公开

    公开(公告)号：US20190393226A1

    公开(公告)日：2019-12-26

    申请号：US16197380

    申请日：2018-11-21

    Applicant: Winbond Electronics Corp.

    Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

    IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/06

    Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.

    Memory device and manufacturing method thereof
    3.
    发明授权
    Memory device and manufacturing method thereof 有权

    公开(公告)号：US10332572B2

    公开(公告)日：2019-06-25

    申请号：US16005698

    申请日：2018-06-12

    Applicant: Winbond Electronics Corp.

    Inventor： Wei-Che Chang ,  Yoshinori Tanaka

    IPC: G11C7/18 ,  H01L27/105 ,  H01L21/027 ,  H01L21/762 ,  G11C5/02 ,  G11C8/14

    Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.

    Memory device and method of fabricating the same
    5.
    发明授权
    Memory device and method of fabricating the same 有权

    公开(公告)号：US09613967B1

    公开(公告)日：2017-04-04

    申请号：US15083302

    申请日：2016-03-29

    Applicant: Winbond Electronics Corp.

    Inventor： Yi-Hao Chien ,  Yoshinori Tanaka ,  Wei-Che Chang

    IPC: H01L27/108

    CPC classification number: H01L27/10894 ,  H01L27/10855 ,  H01L27/10897

    Abstract: A method of fabricating a memory device includes providing a substrate having a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A conductive layer is formed on the substrate in the second region. A top surface of the conductive layer is lower than a top surface of the first dielectric layer. A second dielectric layer is formed on the substrate. A portion of the second dielectric layer and a portion of the conductive layer are removed to form a first opening in the conductive layer and the second dielectric layer in the second region. The first opening exposes a surface of the substrate. A portion of the substrate in the second region is removed to form a trench in the substrate in the second region. A third dielectric layer is formed in the trench and the first opening.

    METHODS OF MANUFACTURING DYNAMIC RANDOM ACCESS MEMORY
    6.
    发明申请
    METHODS OF MANUFACTURING DYNAMIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20220028866A1

    公开(公告)日：2022-01-27

    申请号：US17498765

    申请日：2021-10-12

    Applicant: Winbond Electronics Corp.

    Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

    IPC: H01L27/108 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

    Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190019542A1

    公开(公告)日：2019-01-17

    申请号：US16005698

    申请日：2018-06-12

    Applicant: Winbond Electronics Corp.

    Inventor： Wei-Che Chang ,  Yoshinori Tanaka

    IPC: G11C7/18 ,  H01L21/762 ,  H01L21/027 ,  H01L27/105

    CPC classification number: G11C7/18 ,  G11C5/02 ,  G11C8/14 ,  H01L21/027 ,  H01L21/76224 ,  H01L27/1052 ,  H01L27/10891

    Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.

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