公开(公告)号：US10714482B1

公开(公告)日：2020-07-14

申请号：US16813740

申请日：2020-03-10

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Kazutaka Manabe

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238

Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure.

公开(公告)号：US11688651B2

公开(公告)日：2023-06-27

申请号：US16808410

申请日：2020-03-04

Applicant: Winbond Electronics Corp.

Inventor： Hung-Ming Su ,  Kazuaki Takesako ,  Chun-Chiao Tseng

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L22/34

Abstract: Provided is a semiconductor structure including a substrate, at least two tested structures, an isolation structure, and a short-circuit detection structure. At least two tested structures are disposed on the substrate. The at least two tested structures include a conductive material. The isolation structure is sandwiched between at least two tested structures. The detection structure includes a detecting layer, and the detecting layer is disposed on one of the at least two tested structures, so that a short circuit defect between the at least two tested structures may be identified in an electron beam detecting process, and the detecting layer includes a conductive material. A manufacturing method of the semiconductor structure and a method for detecting a short circuit of the semiconductor structure are also provided.

公开(公告)号：US10217748B2

公开(公告)日：2019-02-26

申请号：US15604684

申请日：2017-05-25

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311

Abstract: A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.

公开(公告)号：US20190019795A1

公开(公告)日：2019-01-17

申请号：US15997706

申请日：2018-06-05

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Huang-Nan Chen ,  Wei-Che Chang

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas.

公开(公告)号：US10083906B1

公开(公告)日：2018-09-25

申请号：US15895568

申请日：2018-02-13

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Wei-Che Chang ,  Kazutaka Manabe ,  Kazuaki Takesako ,  Noriaki Ikeda ,  Yoshinori Tanaka

IPC: H01L27/108 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/5222 ,  H01L23/5228 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.

公开(公告)号：US11018140B2

公开(公告)日：2021-05-25

申请号：US16389322

申请日：2019-04-19

Applicant: Winbond Electronics Corp.

Inventor： Yi-Hao Chien ,  Kazuaki Takesako ,  Kai Jen ,  Hung-Yu Wei

IPC: H01L27/108 ,  H01L21/764

Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.

公开(公告)号：US20200286796A1

公开(公告)日：2020-09-10

申请号：US16808410

申请日：2020-03-04

Applicant: Winbond Electronics Corp.

Inventor： Hung-Ming Su ,  Kazuaki Takesako ,  Chun-Chiao Tseng

IPC: H01L21/66

Abstract: Provided is a semiconductor structure including a substrate, at least two tested structures, an isolation structure, and a short-circuit detection structure. At least two tested structures are disposed on the substrate. The at least two tested structures include a conductive material. The isolation structure is sandwiched between at least two tested structures. The detection structure includes a detecting layer, and the detecting layer is disposed on one of the at least two tested structures, so that a short circuit defect between the at least two tested structures may be identified in an electron beam detecting process, and the detecting layer includes a conductive material. A manufacturing method of the semiconductor structure and a method for detecting a short circuit of the semiconductor structure are also provided.

公开(公告)号：US20180342517A1

公开(公告)日：2018-11-29

申请号：US15604684

申请日：2017-05-25

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/10814 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/7687 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10855 ,  H01L27/10885

Abstract: A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.

公开(公告)号：US10074654B1

公开(公告)日：2018-09-11

申请号：US15942439

申请日：2018-03-31

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Kazutaka Manabe ,  Noriaki Ikeda ,  Wei-Che Chang

IPC: H01L27/108

CPC classification number: H01L27/10808 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876

Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.

公开(公告)号：US20200212044A1

公开(公告)日：2020-07-02

申请号：US16813740

申请日：2020-03-10

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Kazutaka Manabe

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762

Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure.