Invention Grant
- Patent Title: Semiconductor isolation structures having different configurations in different device regions and method of forming the same
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Application No.: US16885286Application Date: 2020-05-28
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Publication No.: US11335770B2Publication Date: 2022-05-17
- Inventor: Yoshinori Tanaka , Wei-Che Chang
- Applicant: Winbond Electronics Corp.
- Applicant Address: TW Taichung
- Assignee: Winbond Electronics Corp.
- Current Assignee: Winbond Electronics Corp.
- Current Assignee Address: TW Taichung
- Agency: JCIPRNET
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/762 ; H01L27/092 ; H01L27/108

Abstract:
Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.
Public/Granted literature
- US20210376074A1 ISOLATION STRUCTURE OF SEMICONDUCTOR AND METHOD OF FORMING THE SAME Public/Granted day:2021-12-02
Information query
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