公开(公告)号：US12224030B2

公开(公告)日：2025-02-11

申请号：US17987435

申请日：2022-11-15

Applicant: Winbond Electronics Corp.

Inventor： Takahiko Sato

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/4096

Abstract: The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

公开(公告)号：US20250048620A1

公开(公告)日：2025-02-06

申请号：US18460610

申请日：2023-09-04

Applicant: Winbond Electronics Corp.

Inventor： Ying-Hung Chen ,  Chun-Chieh Wang ,  Tzu-Ming Ou Yang

IPC: H10B12/00

Abstract: A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.

公开(公告)号：US12215018B2

公开(公告)日：2025-02-04

申请号：US18609571

申请日：2024-03-19

Applicant: Winbond Electronics Corp.

Inventor： Jin-Neng Wu

IPC: B81C3/00 ,  B81B3/00

Abstract: A method for manufacturing package structure is provided, including: providing a substrate having recesses; forming first MEMS chips on the substrate, each with a through-substrate via, and a first sensor or microactuator on the lower surface, located in one of the recesses; forming first intermediate chips on the substrate, each respectively on one of the first MEMS chips, having a through-substrate via, and including a signal conversion unit, a logic operation unit, control unit, or a combination thereof; forming second MEMS chips on the first intermediate chips, each with a through-substrate via, having a second sensor or microactuator on its upper surface, wherein the package structure includes at least one of the first sensor and the second sensor; and forming first capping plates on the second MEMS chips, each providing a receiving space for the second sensor or microactuator on the upper surface of each second MEMS chip.

公开(公告)号：US12213299B2

公开(公告)日：2025-01-28

申请号：US18183158

申请日：2023-03-14

Applicant: Winbond Electronics Corp.

Inventor： Shu-Mei Lee

IPC: H10B12/00

Abstract: A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

公开(公告)号：US12193224B2

公开(公告)日：2025-01-07

申请号：US17591299

申请日：2022-02-02

Applicant: Winbond Electronics Corp.

Inventor： Chun-Lin Li

IPC: H01L27/112 ,  H10B20/25

Abstract: A memory device includes a substrate and an eFuse structure. The substrate includes an array region and an eFuse region and the eFuse region of the substrate has an eFuse trench. The eFuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line, and an eFuse gate electrode. The first gate oxide layer is conformally formed on a surface of the eFuse trench. The doped regions are respectively formed in the substrate on opposite sides outside the eFuse trench, and in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The eFuse gate electrode is formed on the dummy buried word line and in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the eFuse gate electrode.

公开(公告)号：US20250006562A1

公开(公告)日：2025-01-02

申请号：US18754181

申请日：2024-06-26

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hung Lin ,  Hsin-Hung Chou ,  Kao-Tsair Tsai

IPC: H01L21/66 ,  G01R31/28 ,  G03F7/00

Abstract: A layout optimization method and a semiconductor wafer are provided. The method includes: generating adjusted patterns corresponding to a first layout pattern; generating a layout optimization test group according to the adjusted patterns, wherein the layout optimization test group includes first and second clusters of test pattern arrays, the first cluster include first test pattern arrays in accordance with one of the adjusted patterns and different from one another in terms of capacity, and the second cluster include second test pattern arrays in accordance with another one of the adjusted patterns and different from one another in terms of capacity; forming the layout optimization test group on a wafer; performing an electrical inspection on the first and second pattern arrays, and determining a best manufacturing solution from the adjusted patterns according to the electrical inspection.

公开(公告)号：US12176440B2

公开(公告)日：2024-12-24

申请号：US17518270

申请日：2021-11-03

Applicant: Winbond Electronics Corp.

Inventor： Shang-Rong Wu ,  Ming-Che Lin ,  Chung-Hsien Liu

IPC: H01L21/764 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method of forming the semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

公开(公告)号：US20240419339A1

公开(公告)日：2024-12-19

申请号：US18334399

申请日：2023-06-14

Applicant: Winbond Electronics Corp.

Inventor： Koying Huang

IPC: G06F3/06

Abstract: In an aspect, the disclosure is directed to a cell erase method which includes not limited to: initiating an erase operation of a block of memory cells by applying an erase condition to the block of memory cells; performing a first erase verification procedure for at least a portion of the block of memory cells in comparison with a first erase verify voltage; adjusting the first erase verify voltage in response the portion of the block of memory cells having passed the first erase verification procedure; performing a second erase verification procedure for the block of memory cells in comparison with the adjusted erase verify voltage; performing a post program verification procedure for the block of memory cells in comparison with a post program verify voltage to detect leakage current of the block of memory cells; determining whether the adjusted erase verify voltage reaches a final erase verify voltage.

公开(公告)号：US20240387666A1

公开(公告)日：2024-11-21

申请号：US18472286

申请日：2023-09-22

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen HSU ,  Bo-Lun WU ,  Tse-Mian KUO

IPC: H01L29/423 ,  H01L21/768 ,  H10B41/30

Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a floating gate, a dielectric stack, a control gate, and a protective layer. The substrate includes an active region and a peripheral region. The floating gate is disposed on the substrate. The dielectric stack is disposed on the floating gate. The control gate is disposed on the dielectric stack. The protective layer is disposed on the control gate. The protective layer located in the active region has a stepped portion.

公开(公告)号：US20240387175A1

公开(公告)日：2024-11-21

申请号：US18628824

申请日：2024-04-08

Applicant: Winbond Electronics Corp.

Inventor： Chungchen Hsu ,  Tsung-Wei Lin ,  Kun-Che Wu

IPC: H01L21/033 ,  H01L21/3213

Abstract: A semiconductor structure includes a substrate and a target pattern. The target pattern is disposed on the substrate. The top-view pattern of the target pattern includes a main portion and a protruding portion. The main portion and the protruding portion are connected with each other along the long axis of the top-view pattern of the target pattern. The protruding portion is connected to the main portion. The protruding portion includes a first portion located on one side of the long axis. The maximum width of the first portion perpendicular to the long axis is less than half of the maximum width of the main portion.