公开(公告)号：US20200381620A1

公开(公告)日：2020-12-03

申请号：US16428292

申请日：2019-05-31

Applicant: Winbond Electronics Corp.

Inventor： Bo-Lun WU ,  Yi-Hsiu CHEN ,  Ting-Ying SHEN ,  Po-Yen HSU

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.

公开(公告)号：US20210175421A1

公开(公告)日：2021-06-10

申请号：US17115075

申请日：2020-12-08

Applicant: Winbond Electronics Corp.

Inventor： Meng-Hung LIN ,  Bo-Lun WU ,  Po-Yen HSU ,  Ying-Fu TUNG ,  Han-Hsiu CHEN

IPC: H01L45/00 ,  H01L27/24

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

公开(公告)号：US20200321521A1

公开(公告)日：2020-10-08

申请号：US16839270

申请日：2020-04-03

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen HSU ,  Bo-Lun WU ,  Ting-Ying SHEN

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes a substrate having an array region and a peripheral region. A plurality of memory cells and a gap-filling dielectric layer overlying the memory cells are located on the substrate and in the array region. A buffer layer only in the array region covers the gap-filling dielectric layer, and its material layer is different from that of the gap-filling dielectric layer. A first low-k dielectric layer is only located in the peripheral region, and its material is different from that of the buffer layer. A dielectric constant of the first low-k dielectric layer is less than 3. A top surface of the first low-k dielectric layer is coplanar with that of the buffer layer. A first conductive plug passes through the buffer layer and the gap-filling dielectric layer and contacts one of the memory cells.

公开(公告)号：US20210043836A1

公开(公告)日：2021-02-11

申请号：US16534608

申请日：2019-08-07

Applicant: Winbond Electronics Corp.

Inventor： Bo-Lun WU ,  Shih-Ning TSAI ,  Po-Yen HSU

IPC: H01L45/00

Abstract: A memory device includes a first electrode, a resistive switching layer, a cap layer, a protective layer, and a second electrode. The resistive switching layer is disposed over the first electrode. The cap layer is disposed over the resistive switching layer, wherein the bottom surface of the cap layer is smaller than the top surface of the resistive switching layer. The protective layer is disposed over the resistive switching layer and surrounds the cap layer. At least a portion of the second electrode is disposed over the cap layer and covers the protective layer.

公开(公告)号：US20170256711A1

公开(公告)日：2017-09-07

申请号：US15449632

申请日：2017-03-03

Applicant: Winbond Electronics Corp.

Inventor： Yi-Hsiu CHEN ,  Ming-Hung HSIEH ,  Po-Yen HSU ,  Ting-Ying SHEN

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 μm. A top electrode is formed on the transition metal oxide layer.

公开(公告)号：US20150280119A1

公开(公告)日：2015-10-01

申请号：US14474931

申请日：2014-09-02

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen HSU ,  Hsiu-Han LIAO ,  Shuo-Che CHANG ,  Chia Hua HO

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1641

Abstract: Structures and formation methods of memory devices are provided. The memory device includes a first electrode, a second electrode, and a resistive layer positioned between the first electrode and the second electrode. The resistive layer has a crystalline portion. A volume ratio of the crystalline portion to the resistive layer is in a range from about 0.2 to about 1.

Abstract translation: 提供了存储器件的结构和形成方法。 存储器件包括位于第一电极和第二电极之间的第一电极，第二电极和电阻层。 电阻层具有结晶部分。 结晶部分与电阻层的体积比在约0.2至约1的范围内。

公开(公告)号：US20240387666A1

公开(公告)日：2024-11-21

申请号：US18472286

申请日：2023-09-22

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen HSU ,  Bo-Lun WU ,  Tse-Mian KUO

IPC: H01L29/423 ,  H01L21/768 ,  H10B41/30

Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a floating gate, a dielectric stack, a control gate, and a protective layer. The substrate includes an active region and a peripheral region. The floating gate is disposed on the substrate. The dielectric stack is disposed on the floating gate. The control gate is disposed on the dielectric stack. The protective layer is disposed on the control gate. The protective layer located in the active region has a stepped portion.

公开(公告)号：US20240147726A1

公开(公告)日：2024-05-02

申请号：US18495339

申请日：2023-10-26

Applicant: Winbond Electronics Corp.

Inventor： Bo-Lun WU ,  Po-Yen HSU ,  Tse-Mian KUO

IPC: H10B43/30

CPC classification number: H10B43/30

Abstract: A method of forming a memory structure is provided. The method includes providing a substrate, wherein the substrate has a plurality of isolation structures, and the isolation structures include a plurality of first protrusions protruding above the substrate; replacing the first protrusions with a plurality of second protrusions to define a plurality of predetermined regions of floating gates between the second protrusions. The replacing step includes forming an insulation filling material between the first protrusions and on the substrate, and performing a patterning process to the insulation filling and the first protrusions to form second protrusions to define the predetermined regions of the floating gates, and forming a plurality of floating gates in the predetermined regions of the floating gates.

公开(公告)号：US20220293851A1

公开(公告)日：2022-09-15

申请号：US17525079

申请日：2021-11-12

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen HSU ,  Bo-Lun WU ,  Tse-Mian KUO

IPC: H01L45/00

Abstract: A semiconductor structure includes a substrate, a first electrode, a vacancy supply layer, a sidewall barrier layer, an oxygen reservoir layer, a resistive switching layer, and a second electrode. The first electrode is disposed on the substrate. The vacancy supply layer is disposed on the first electrode. The sidewall barrier layer is disposed on the first electrode. The oxygen reservoir layer is disposed on the first electrode. The sidewall barrier layer is disposed between the oxygen reservoir layer and the vacancy supply layer. The resistive switching layer is disposed on the vacancy supply layer. The second electrode is disposed on the resistive switching layer.

公开(公告)号：US20220069210A1

公开(公告)日：2022-03-03

申请号：US17010435

申请日：2020-09-02

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen HSU ,  Bo-Lun WU ,  Tse-Mian KUO

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first dielectric layer, a bottom electrode, a resistance switching layer, an oxygen exchange layer, a barrier layer and a top electrode. The first dielectric layer is disposed on the substrate. The bottom electrode is disposed on the first dielectric layer. The resistance switching layer is disposed on the bottom electrode. The oxygen exchange layer is disposed on the resistance switching layer. A contact area between the oxygen exchange layer and the resistance switching layer is smaller than a top surface area of the resistance switching layer. The barrier layer is disposed on the oxygen exchange layer. The top electrode is disposed on the barrier layer.