公开(公告)号：US20200350268A1

公开(公告)日：2020-11-05

申请号：US16398278

申请日：2019-04-30

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Jin-Neng Wu ,  Chun-Hung Lin ,  Hsin-Hung Chou

IPC: H01L23/00

Abstract: A wire bonding structure and a method of manufacturing the same are provided. The wire bonding structure includes a bonding pad structure, a protection layer and a bonding wire. The bonding pad structure includes a bonding pad and a conductive layer. The bonding pad has an opening. The conductive layer is electrically connected to the bonding pad. At least a portion of the conductive layer is located in the opening of the bonding pad and laterally surrounded by the bonding pad. The protection layer at least covers a portion of a surface of the bonding pad structure. The bonding wire is bonded to the conductive layer of the bonding pad structure.

公开(公告)号：US10483235B2

公开(公告)日：2019-11-19

申请号：US15057973

申请日：2016-03-01

Applicant: Winbond Electronics Corp.

Inventor： Yu-Cheng Chiao ,  Tung-Yi Chan ,  Chen-Hsi Lin ,  Chia Hua Ho ,  Meng-Chang Chan ,  Hsin-Hung Chou

IPC: H01L25/065

Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

公开(公告)号：US11063010B2

公开(公告)日：2021-07-13

申请号：US16264684

申请日：2019-02-01

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Jin-Neng Wu ,  Hsin-Hung Chou ,  Chun-Hung Lin

IPC: H01L23/00

Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

公开(公告)号：US20250006562A1

公开(公告)日：2025-01-02

申请号：US18754181

申请日：2024-06-26

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hung Lin ,  Hsin-Hung Chou ,  Kao-Tsair Tsai

IPC: H01L21/66 ,  G01R31/28 ,  G03F7/00

Abstract: A layout optimization method and a semiconductor wafer are provided. The method includes: generating adjusted patterns corresponding to a first layout pattern; generating a layout optimization test group according to the adjusted patterns, wherein the layout optimization test group includes first and second clusters of test pattern arrays, the first cluster include first test pattern arrays in accordance with one of the adjusted patterns and different from one another in terms of capacity, and the second cluster include second test pattern arrays in accordance with another one of the adjusted patterns and different from one another in terms of capacity; forming the layout optimization test group on a wafer; performing an electrical inspection on the first and second pattern arrays, and determining a best manufacturing solution from the adjusted patterns according to the electrical inspection.

公开(公告)号：US11322438B2

公开(公告)日：2022-05-03

申请号：US17015012

申请日：2020-09-08

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Hsin-Hung Chou ,  Chun-Hung Lin

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure including a lead frame structure, a die, an adhesive layer, and at least one three-dimensional (3D) printing conductive wire is provided. The lead frame structure includes a carrier and a lead frame. The carrier has a recess. The lead frame is disposed on the carrier. The die is disposed in the recess. The die includes at least one pad. The adhesive layer is disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier. The 3D printing conductive wire is disposed on the lead frame, the adhesive layer, and the pad, and is electrically connected between the lead frame and the pad.

公开(公告)号：US20220077051A1

公开(公告)日：2022-03-10

申请号：US17015012

申请日：2020-09-08

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Hsin-Hung Chou ,  Chun-Hung Lin

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00

Abstract: A package structure including a lead frame structure, a die, an adhesive layer, and at least one three-dimensional (3D) printing conductive wire is provided. The lead frame structure includes a carrier and a lead frame. The carrier has a recess. The lead frame is disposed on the carrier. The die is disposed in the recess. The die includes at least one pad. The adhesive layer is disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier. The 3D printing conductive wire is disposed on the lead frame, the adhesive layer, and the pad, and is electrically connected between the lead frame and the pad.

公开(公告)号：US10818497B2

公开(公告)日：2020-10-27

申请号：US15681436

申请日：2017-08-21

Applicant: Winbond Electronics Corp.

Inventor： Yen-Jui Chu ,  Hsin-Hung Chou ,  Ming-Chih Tsai

IPC: H01L21/28 ,  H01L23/00 ,  H01L25/065 ,  B81C1/00 ,  H01L21/3213 ,  H01L29/49

Abstract: The present invention provides a patterned structure for an electronic device and a manufacturing method thereof. The patterned structure includes a patterned layer, a blocking structure, a cantilever structure, and a connection structure. The patterned layer is disposed on a substrate. The blocking structure is disposed on the substrate at one side of the patterned layer, wherein a thickness of the blocking structure is smaller than a thickness of the patterned layer. The cantilever structure is disposed on the substrate and located between the patterned layer and the blocking structure. The cantilever structure is connected with the patterned layer and the blocking structure. The connection structure is connected between the patterned layer and the substrate at one side of the patterned layer, and located on the cantilever structure and the blocking structure.

公开(公告)号：US12148627B2

公开(公告)日：2024-11-19

申请号：US17480757

申请日：2021-09-21

Applicant: Winbond Electronics Corp.

Inventor： Hsin-Hung Chou ,  Tsung-Wei Lin ,  Kao-Tsair Tsai

IPC: H01L21/3213 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66 ,  H10B41/30

Abstract: A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack.

公开(公告)号：US11335568B2

公开(公告)日：2022-05-17

申请号：US16872760

申请日：2020-05-12

Applicant: Winbond Electronics Corp.

Inventor： Ting-Wei Wu ,  Cheng-Ta Yang ,  Hsin-Hung Chou

IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/033

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.

公开(公告)号：US09881901B2

公开(公告)日：2018-01-30

申请号：US15015919

申请日：2016-02-04

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Yu-Cheng Chiao ,  Tung-Yi Chan ,  Chen-Hsi Lin ,  Chia Hua Ho ,  Meng-Chang Chan ,  Hsin-Hung Chou

IPC: H01L21/44 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2225/06506 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.