公开(公告)号：US11765881B2

公开(公告)日：2023-09-19

申请号：US18076419

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L23/522 ,  H10B12/00 ,  H01L21/768

CPC classification number: H10B12/0335 ,  H01L21/76816 ,  H10B12/01 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US20210272962A1

公开(公告)日：2021-09-02

申请号：US17324114

申请日：2021-05-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US11018006B2

公开(公告)日：2021-05-25

申请号：US16592773

申请日：2019-10-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/02 ,  H01L27/108 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US20210043684A1

公开(公告)日：2021-02-11

申请号：US17082034

申请日：2020-10-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tzu-Tsen Liu ,  Tsung-Ying Tsai ,  Chien-Ting Ho

IPC: H01L27/24 ,  H01L27/108 ,  H01L21/02 ,  H01L21/764

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

公开(公告)号：US20190333913A1

公开(公告)日：2019-10-31

申请号：US16504314

申请日：2019-07-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Shih-Fang Tzou

IPC: H01L27/088 ,  H01L27/108 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US10276577B2

公开(公告)日：2019-04-30

申请号：US15884399

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/108

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

公开(公告)号：US20190115352A1

公开(公告)日：2019-04-18

申请号：US16216954

申请日：2018-12-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L27/108

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

公开(公告)号：US20180260510A1

公开(公告)日：2018-09-13

申请号：US15479271

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Chien-Ting Ho ,  Li-Wei Feng ,  Emily SH Huang

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/108

CPC classification number: G06F17/5077 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

公开(公告)号：US20180211964A1

公开(公告)日：2018-07-26

申请号：US15873909

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tzu-Tsen Liu ,  Tsung-Ying Tsai ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L27/24 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/764 ,  H01L27/10847 ,  H01L27/249

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

公开(公告)号：US20230097175A1

公开(公告)日：2023-03-30

申请号：US18076419

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108 ,  H01L21/768

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.